资源列表
oscillator
- CODE FOR ON CHIP OSCILLATOR IMPLEMENTATION IN ALTERA MAX2 SERIES CPLD
crc5
- CRC 5 encription and decription module. Operates with serial input data, CRC output is 5bits register. If you decoding CRC the input is valid when output is set to 00000 .-CRC 5 encription and decription module. Operates with serial input data, CRC o
4_COMP
- 使用硬件实现,效率较高的乘法器,通过FPGA验证的
基于vhdl的二进制转BCD码的设计
- 基于vhdl的二进制转BCD码的设计，已经经过调试，可直接使用,Vhdl based on binary code to BCD design, has been testing can be used directly
58
- 5/8分频器，实现分频功能，受外部周期信号激励的震荡，其频率恰为激励信号频率的纯分数，都叫做分频。-5/8frequency demultiplier
DATA_scramble
- 扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
seg71
- ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０--7 实验的目的是向用户介绍多个数码管动态显示的方法。 动态显示的方法是，按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。-7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to th
Decoy
- 外部 FIFO 的控制 verilog语言-verilog FIFo
mapper
- vhdl code for mapping the real and quadrature QAM Symbol
led
- 学习单片机的很好历程，led显示，已经调试通过-Learning a good SCM process, led display, has been through debugging
dianzizhong
- 用VHDL语言编写的数字电子钟的代码，在quartus上运行即可-Digital clock using VHDL language code can be run on in the quartus
ads7841_control
- 本程序是fpga控制ads7841采样，fpga中用状态机来写时序，亲测可用-This procedure is fpga control ads7841 sampling, fpga using state machine to write timing, pro-test available