资源列表
synd
- Syndrome calculator basic unit for reed solomon decoder in verilog language
hmwk3try.vhd
- Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined variable
alu
- 可以实现十六种算术运算和逻辑运算的VHDL代码哦，ISE上编译仿真可以运行-Can achieve sixteen kinds of arithmetic and logic operations of the VHDL code Oh, ISE compiled simulation can be run on
LED_FND_LCD
- Hi, This Verilog practice code-Hi, This is Verilog practice code
decode_for_m68008
- -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X\"00000\" to X\"01FFF\" -- csbar(1) : X\"40000\" to X\"43FFF\" -- csbar(2) : X\"08000\" to X\"0AFFF\" -- csbar(3) : X\"E000
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
fft
- fft源代码，希望对大家有用，谢谢 fft源代码，希望对大家有用，
div
- 除法器的电路设计,基本的思想是减法:从最高位(除符号位)开始,减去除数,得到商. -Divider circuit design, the basic idea of subtraction: from the highest bit (except the sign bit), and subtract the divisor, the quotient.
counter_program
- 8位计数器程序，可预置的8位计数器程序的主要部分分析，内有程序详细注释-8-bit counter program, 8-bit counter can be preset for major part of the analysis, detailed comments within the program
fifo
- first in first out buffer
TXcontrol
- 在一个具有编解码，调制解调等的简单通信系统的硬件仿真中，发送端的时隙控制的VHHL源码-In emulation of a codec, modem, etc. have a simple communication system, the sender of the control slot VHHL source
MyCounter
- 可自由配置的通用计数器，我设计的时候一直在用