资源列表
signal-process_based-FPGA
- 给予FPGA内核处理语音信号，外围部件有AD/DA芯片，RTL级实现对信号的采集处理到输出-signal process_based FPGA
isen
- 基于FPGA设计工具Xilinx ISE 编写的程序代码 包含有计数器，状态转移码，交通灯，时序约束等程序-Program code written based on FPGA design tools Xilinx ISE includes procedures such as counters, state transition code, traffic lights, timing constraints
VHDL_RAM_FIFO_ROM
- VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer
MT9P031_CONFIG
- 自己做的智能相机,CMOS的配置功能,是经过验证的,可以使用.(The smart camera that you do, the configuration function of CMOS)
Digital_Design_of_Signal_Processing_Systems-_Dr_S
- digital system design
xapp443
- XILINX的一个以太网例程，包含以太网内核的建立以及仿真过程，是XAPP443的例子-Routines of the XILINX a Ethernet, including Ethernet kernel establish and simulation process XAPP443 example
FPGA-CPLD_DesignTool(8-9-10)
- FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载-FPGA-CPLD_DesignTool (8-9-10) requested the source code to their peers in need Friends Download
DDS2
- 基于Verilog语言的正弦波的产生，应用了基于直接数字频率合成器的方法。-Verilog language generated based on the sine wave, the frequency of application of the direct digital synthesizer based methods.
S03_基于ZYNQ的DMA与VDMA的应用开发
- VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
Hua-wei-FPGA
- 华为FPGA设计全套，我导师做课题时候给我的。-Huawei complete FPGA design, when I do the subject mentor to me.
CIC_filter
- 抽取:(接收端) 中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。 插值:(发送端) 基带信号上变频到1M，采样率是2.5M，采用CIC滤波器进行升采样率处理。 注释：升采样率或者降采样率不会改变原始信号的中心频率，但是频谱分布会发生改变。-Extraction: (receiver) IF signal 20M (sampling rate is 50M) down-conversion signal M
spimasterslaveceshi2
- 串口主机和从机进行正常通信的FPGA实现，编译已通过。-Master and slave serial communication on FPGA normal, compiled has passed.