资源列表
GLSA
- verficaiton acceration tools for linux for FPGA
vga_7_0728
- 用vga显示数字钟，通过串口可以控制时间显示(With vga digital clock, through the serial port can control the time display)
adv7390_test_U29_auto
- ADV7390芯片for FPGA XC7K325T的测试程序，内包含芯片的SPI配置参数，程序烧录进FPGA后接BNC线可以在监视器上看到滚动的彩条。- ADV7390 for chip FPGA testing procedures XC7K325T, SPI configuration parameters included in the chip, the program downloaded into FPGA connected to the BNC line can se
vedio_format
- 本代码是bt1120 格式产生以及转换为rgb源代码，开发环境为vhdl。-this code describe the bt1120 generator and change form soure code.
adder
- 选择相加器，可以通过拨动开关控制输入1，输入2，输入3的相加顺序。-Choose the summator, can through the toggle switch control input 1, type 2, input the addition order of 3.
VHDLcircuitdesign
- 《VHDL电路设计技术》，对于VHDL语言爱好者来说是一本很不错的参考资料！欢迎下载！-《VHDL circuit design technology》， VHDL language for lovers is a very good reference! Welcome to download!
cal
- 运用quartusII vhdl语言做成的计算器-Made use of quartusII vhdl calculator language
fft3
- 是用verilog写的FFt源码，通过编译基本是正确，希望对大家有所帮助-Is written FFt verilog source code, compile basic right, we want to help
512点FFTVerilog实现
- 关于FFT Verilog代码实现的源代码
time_three
- 基于sopc的三个定时器的三种应用，希望可以帮到学习FPGA的人，谢谢！-The three timer-based sopc three applications, the desire to help people learn FPGA, thank you!
DDR2_Control
- 参考例程之Verilog之实现DDR2时序控制实现，ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)
BS
- 用EDA设计ROM和RAM及其应用，用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display