资源列表
async_transmitter
- An Asynchronous transmitter to be used in digital oscilloscope
shift_reg_sp
- this VHDL Progran get a SCLK(seril CLock) and a WCLK(Word CLOCK) with a serial data line and return a 64nits Parallel data.
JKdff
- 基于VHDL语言设计的边沿JK触发器，及相应的仿真波形-VHDL language design based on the edge of JK flip-flop, and the corresponding simulation waveforms
Gap_Finder
- To find the distance between two input 4 bits and output it in 2 bits
counter
- counter design in vhdl
Vhdl1
- calculating of iD & iQ, with ia & ib in 2 s complement
dual_port_rom
- dual port ram, it is having two data lines and two address lines at a time we can access two data from the two data lines
PWM
- 用于红外脉冲调制发射的程序，可将信号调制为38khz-hongwai fashe
dualram
- 本文件给出了一种双口RAM的代码，开发语言为verilog。测试可用，欢迎下载-This document gives a dual-port RAM code verilog development language. Test is available, welcome to download
load--clr-register
- 带load、clr等功能的寄存器 VHDL语言编写，亲自运行，成功-Register VHDL language, with features such as load, clr personally run
ADtest
- FPGA与ADS822通信，控制ADS822采集波形，并通过DA输出显示-FPGA communicates with ADS822, control ADS822 waveform acquisition and output display by DA