资源列表
NCO_test
- FPGA的压控振荡器NCO完整Verilog工程代码，测试输出1KHZ sin波。signaltap抓取没问题。-VCO NCO complete FPGA Verilog code engineering, test output 1KHZ sin wave. signaltap crawl no problem.
8051
- alter公司的mcu核，8051ip核，为quartus2设计，其他应该兼容 -alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
NIOS_lcd12864
- 基于NIOS II系统的12864LCD的读写。-12864LCD NIOS II system based on reading and writing.
FSK调制解调
- 用Verilog语言 在 Quarters 平台 实现FSK调制与解调(The realization of FSK modulation and demodulation on the Quarters platform in Verilog language)
fpga-nois
- 里面包含fpga的4个noic核 verilog(i2c,rs232,can,8051)。测试过不错-Which contains the four noic nuclear fpga verilog (i2c, rs232, can, 8051). Tested good
FPGA_EP4C
- Scematic and Verilog Examples for generic Cyclone iV board.
基于FPGA自治混沌网络量化真随机数代码
- 基于FPGA自治布尔混沌网络，量化真随机数。可通过例化多组网络，产生高带宽真随机数，根据FPGA性能，自重随机数带宽达数G.
FPGA_developer
- FPGA开发攻略，对提高你的FPGA开发水平，编写高效的FPGA有很大的帮助，最好有FPGA开发基础-FPGA development Raiders , raising the level of your FPGA development, preparation and efficient FPGA great help, preferably based FPGA development
qiangda
- EDA课程设计，是四路智力抢答器的vdhl程序，里面还有我自己录课程视频。仅作为参考！-EDA curriculum design, is a quad of vdhl intellectual Responder program, which was recorded courses and my own video. Only as a reference!
qiangda
- EDA课程设计智力抢答器 四路抢答器的设计以及程序和视屏 软件运行环境是：Quartus 9.1-EDA curriculum design intelligence Responder four answering device design and process and Screen software operating environment is：Quartus 9.1
ad80518253
- fft 单片机+fpga+8051core-fft MCU+ fpga+8051 core
IFFT
- 使用ISE开发环境实现802.11a物理层OFDM系统中逆fft模块-ISE development environment inverse fft module 802.11a physical layer OFDM system