资源列表
秒表
- 基于VHDL语言实现秒表的计时、倒计时的功能。(The function of timing and countdown of the stopwatch based on VHDL language.)
xapp879
- pll 动态从配置锁相环时钟输出，为官网demo(pll reconfig xilinx vivado)
vip_ex2
- 特权同学开发板上的例程，DDR2控制器集成与读写测试(The routines on the privileged students' development board, DDR2 controller integration and reading and writing tests)
Ethernet_usd_send_quartus
- Ethernet_UDP_send_quartus
Hydrangeas
- ferferf erferfref yhythy wedwefwefwefwefw grtgertegwerg
10_rom_test
- 讲解赛灵思Spartant_6系列FPGA的ROM IP核的调试过程，供大家参考学习(Explain Xilinx Spartant_6 Series FPGA ROM IP core debugging process, for your reference learning)
07_uart_test
- 利用FPGA的并行方式调试UART，与单片机的调试方式做比较(Using FPGA to debug UART in parallel, make comparison with the way of MCU debugging)
27_adda_test
- 黑金FPGA的ADDA调试例程，与大家一起共同学习进步，主要讲的是8位ADDA的调试。(ADDA debugger routines with black gold FPGA, and learn together with everyone to learn progress, mainly about the debug of 8 ADDA.)
PLL_test
- 用FPGA实现锁相环分频，将基准时钟频率通过PLL核分频生成多种时钟生成。(Phase-locked loop with FPGA to achieve frequency division, the frequency of the reference clock through the PLL core frequency to generate a variety of clock generation.)
LED
- 利用verilog语言，在FPGA开发版上点亮LED灯(Using verilog language, LED lights on the FPGA development version)
Asynchronous FIFO Architectures
- 老外的经典异步FIFO结构讲解，一共三个部分。(Asynchronous FIFO Architectures Vijay A. Nebhrajani)
csa_codes
- carry_select_adder for 16-bit in verilog