资源列表
hvdl
- 实现60秒秒表功能，代码简单，可扩展，可操作，已在FPGA开发板上实现-Achieve 60 seconds stopwatch function, the code is simple, scalable, operable in FPGA development board to achieve
rxd_control
- 串口接收控制模块联合uart——rxd_interface使用-uart rxd contrl Verilog
mif_generation
- 利用C生成quartus中ROM所需用的mif或者hex文件，以正弦信号为例-Using C to generate .mif for quartus ii
traffic
- 交通灯的控制，很简单的一个东西而已，仅用来开通账户-Traffic light control, a very simple things, you know, only used to open accounts
LED
- VHDL LED七段译码程序,程序为txt格式，请自行另存为vdh后缀的文件-VHDL LED seven-segment decoding process, procedures txt format, please use the Save As vdh file suffix
led_0_7
- 与键盘扫描功能相对应，实现7段数码管的显示功能，在单片机中有较大用处。verilog-fullfill the function of displaying in verilog language. You can use it combined with keyboard scanning
PRF_CTL
- 产生时序脉冲组，设计人员可以根据自己的需要，改变相应的数值，可以得到自己想要的脉冲组-Generates timing pulses, designers can according to their needs, change the appropriate values, you can get what you want in the pulse group
led
- 流水灯，通过时钟控制，每个时间显示不同颜色，共有32中颜色-Water lamp, the clock control, each time display different colors, a total of 32 colors
shuma.rar
- 数码管动态显示程序，verilog的，已经调试成功,verilog
sdh1
- 本段代码是关于SDH帧的操作的一段VHDL的代码。 主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame he
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog