资源列表
memoryuse
- Verilog HDL语言在FPGA实现中的存储器的使用详细说明-Verilog HDL language in the FPGA memory of the use of detailed
vhdl_sw_lr
- 我自己写的vhdl程序，内有画图器，ram 和控制ram。还有test bentch。-I wrote it myself vhdl procedures, which are drawing device, and control of ram ram. There bentch test.
VCDwtHDLV
- < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘
03034
- verilog中的一个不用状态机和决断函数就可以实现多重函数赋值的例子，希望对你用帮助。-verilog of a state machine and no decisive function could achieve multiple functions assigned to the case, you want to help.
modelsim_guide_cn
- modelsim操作指导 很适合入门 有实例-modelsim operation guidance is very suitable example of a portal
sourceIIR6
- IIR 六阶数字滤波器的 VHD L 描述-six-IIR Digital Filter Volume L Descr iption
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
liangzhu
- 基于max—plus2开发环境，设计的《梁祝》演奏曲-based max-plus2 development environment, the design of the "Butterfly Lovers" concert song
PWMnios
- niosPWM可以在SOPC builder中实现PWM功能的自定制，通过PWM口可实现对电机的调速。-niosPWM SOPC builder can achieve PWM function of customized, PWM through the mouth can be realized right motor speed control.
jiaotongdengcodes
- 实例制作的一个有关交通灯的VHDL代码，从各模块到顶层文件的代码一一列出，详细周到，附带仿真波形图和芯片管脚锁定的相关内容，绝对物超所值。-produced an example of the traffic light VHDL code, from the module to the top of the document sets out a code on January 1, thoughtful details, fringe simulation waveform map and
VHDLdesignURA
- 用VHDL编写的URAT程序，适合教学或自学使用-VHDL URAT prepared by the procedures for the use of teaching or self -
VHDLdesignGame
- 用VHDl设计一个小游戏的例子，适合教学或自学使用-VHDl design with a small example of the game, suitable for use or self-teaching