资源列表
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-p
traffic_lamp
- 用verlog语言编的又一个很好的综合实验(交通灯的控制),特别适合于FPGA/CPLD的初学者-verlog language used is an addendum to the good of the experiment (traffic light control), particularly suitable for FPGA / CPLD beginners
digital_clock
- 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA / CPLD beginners
fpga(CAN)
- fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。-fpga CAN Bus Controller source, each with explanatory documents on the use of methods.
IIS_VHDL
- VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
cfft
- 参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
vhdltoverilog
- vhdl to verilog语言的编程设计，很有参考价值。-vhdl to verilog programming language design, great reference value.
chap12
- 《Verilog HDL 程序设计教程》9-"Verilog HDL Design Guide" 9
chap11
- 《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8
chap10
- 《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7
chap9
- 《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6
chap8
- 《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5