资源列表
Coding Styles for if Statements and case Statement
- Coding Styles for if Statements and case Statements
CummingsSNUG2002SJ_FIFO1
- Simulation and Synthesis Techniques for Asynchronous FIFO Design
config_controller
- 用VHDL硬件描述语言实现的对FPGA(Cyclone II)的配置的VHDL源代码。-VHDL hardware descr iption language for FPGA (Cyclone II) configurations VHDL source code.
Cadence_manual_1.2
- Cadence_manual_1.2.pdf
mealy FSM
- mealy fsm 和moore fsm-mealy Fsm and moore Fsm
xsoc-beta-093
- This free cpu-ip! use verilog
uart from opencores
- 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
8位数字频率计
- 数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
35_486_bus
- 请注意: 本例的源描述包含文件类型,在学习版上不能编译及模拟, 如果您需要对此描述进行编译及模拟,请与北京理工大学 ASIC研究所联系。 另外,此例与第75例是同一个电路的不同部分的描述,可以 一起参考这两个例子的描述。-Please note : The cases include the descr iption of the source file type, version of the study can not be compiled and simulation, if
Xilinx公司网站下的SDRAM Controller的参考设计
- Xilinx公司网站下的SDRAM Controller的参考设计,经过验证-Xilinx website of SDRAM Controller reference design, validated
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
能综合的YCrCb2RGB模块(verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块(verilog)_采用3级流水线,用fpga做小数运算,还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology