资源列表
mb
- 基于Proasic3 startkit 开发板，用verilog语言描述的一个秒表计数器。-Based the ProASIC3 StartKit development board, using Verilog language descr iption of a stopwatch counter.
div5
- 用verilog描述的任意分频器，包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
z8051
- 在libero8.1环境下，用Verilog描述的8051内核，可以包括各个基本模块，可以仿真。-In the libero8.1 environment described in Verilog 8051 core, including the basic module can be simulated.
uart
- 用verilog描述的uart收发模块，比较经典。-With the the UART transceiver module Verilog described, classic.
rankSort
- 基于MPI的并行快速排序算法，VS2010编译运行通过-MPI-based parallel quick sort algorithm, VS2010 compiled to run through
QuickSort
- MPICH2实现的并行快排算法，VS2005编译通过-The MPICH2 implementation fast parallel row algorithm VS2005 compiled by
Matrix
- 矩阵相乘并行计算程序 C——C++边写 已实现-Matrix multiplication parallel program
SX
- 基于Proasic3 startkit开发板，描述了8位地址锁存芯片74ls259和Uart接受模块，通过这两个模块来控制开发板上的led.-Based on the the ProASIC3 StartKit development board, describes the 8-bit address latch chip 74LS259 and the UART receiving module, to control development board led by these two m
ofdm
- 基于simulink的OFDM系统仿真 QPSK仿真 64点仿真-QPSK to simulation 64 points simulation simulink-based OFDM system simulation
uartfifo
- 以Proasic3 Start kit开发板为平台，介绍了FIFO的基本功能。-ProASIC3 Start Kit development board as a platform to introduce the basic functions of the FIFO.
Neural_Net1922868102005
- Nueral Nework algorithm
Genetic_Al2085099292007
- GENETIC ALGORITHM USING C-GENETIC ALGORITHM USING C++