文件名称:design_4
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利用48M时钟信号定时得到事先设置好的延时,通过延时信号接到蜂鸣器发出提示声音。主持人,抢中,抢答时间到,答题时间到,四个信号分别触发计数延时,最后把得到的三个报警信号相与(因为系统设置为低电平有效),作为最后的报警信号。 每个触发延时计时,在触发信号无效(‘1’)时,将计数值归零,触发信号有效时(‘0’),开始记时钟个数,记到一定(根据需要事先设置好)个数,就得到延时时间(延时时间=时钟个数*时钟周期),时间延时报警信号无效,得到一定时间的报警信号。
-48M clock signal timing delay set well in advance through the the delay signal received buzzer beep sound. Moderator, looting, to answer in time, answer time, four signals trigger count delay, the last three alarm signal phase and (because the system is set to active low), as the last of the alarm signal . Each trigger delay time, when the trigger signal is invalid (' 1 ' ), the count value is zero, and when the trigger signal is effective (' 0' ), starts counting the number of clocks, credited to a certain pre-set (according to need) number, to obtain the delay time (delay time = the number of clocks* clock cycle), the time delay an alarm signal is invalid, and to obtain a certain time of the alarm signal.
-48M clock signal timing delay set well in advance through the the delay signal received buzzer beep sound. Moderator, looting, to answer in time, answer time, four signals trigger count delay, the last three alarm signal phase and (because the system is set to active low), as the last of the alarm signal . Each trigger delay time, when the trigger signal is invalid (' 1 ' ), the count value is zero, and when the trigger signal is effective (' 0' ), starts counting the number of clocks, credited to a certain pre-set (according to need) number, to obtain the delay time (delay time = the number of clocks* clock cycle), the time delay an alarm signal is invalid, and to obtain a certain time of the alarm signal.
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4基于FPGA的报警器设计和仿真.docx
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