用Verilog HDL设计3线-8线译码器，ena是译码器的使能控制端，当ena=1时译码器工作，ena=0时译码器被禁止，8个输出均为高电平

用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disabled, 8 outputs are high 8D latch with tri-state output level using Verilog HDL design.