Abstract—This paper presents a Viterbi-based test compression

algorithm/architecture that provides high encoding efficiency

and scalability with respect to the number of test channels. The

proposed scheme finds a set of compressed test vectors using the

Viterbi algorithm instead of solving linear equations. By assigning

a cost function to the branch metric of the Viterbi algorithm,

an optimal compressed vector is selected among the possible

solution set. This feature enables high flexibility to combine

various test requirements such as low-power compression and/or

improving capability to repeat test patterns. The proposed onchip

decompressor follows the structure of Viterbi encoders

which require only one input channel. Experimental results

on test volume show improvement benchmark

yields e