搜索资源列表
AESverilog
- AES加密算法的Verilog语言实现，通过编译-AES encryption algorithm in Verilog Implementation
4x4_bits_Booth_Algorithm
- Verilog写的booth算法，是微机原理的基本算法，对Verilog的入门有帮助，包含代码和报告-Booth algorithm written in Verilog is the basic principle of computer algorithms, Verilog entry helpful, the report contains the code and
etd-0407109-183702-81-001[1]
- 文章介绍了YUV向RGB颜色空间转换的硬件电路实现算法.在高基乘法算法基础上,建立了参数化高基乘法算法模型,并给出了Verilog HDL描述 小数乘法的整数乘法近似和近似误差给予了详细的讨论.采用乘法单元复用的设计结果将在两个时钟周期内完成YUV向RGB的颜色空间转换.-This paper introduces the YUV to RGB color space conversion hardware algorithm. Matrix multiplication algorithm i
my_kmp_matching
- KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
Verilog
- 一些verylog算法法，很好的文章，建议初学者学习-Some verylog algorithm method, a very good article, it is recommended for beginners
add32
- 32位加法器，基于vhdl语言，主要用于测试算法-32-bit adder, based on the vhdl language, mainly used for testing algorithms
32bitcpu
- 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations righ
cordic4_2
- CORDIC算法相角模式HDL实现源码，Verilog HDL书写，10级迭代，仿真验证通过。-CORDIC algorithm implementation phase model HDL source code, Verilog HDL writing, 10 iterations, the simulation is verified.
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
cf_fft_1024_8
- 1024点的fft算法verilog实现程序，主要是通过verilog来实现fft算法- 1024 spot fft algorithm verilog realizes the procedure
verilog
- 這是一個除法器演算法，是利用移位的方式進行除法運算-This is a divider algorithm is the use of division shift the way
scoreboard
- MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
csa_verilog_rtl
- CSA加扰算法verilog实现，代码经过fpga验证，可以正确实现该算法。-CSA verilog rtl codeing
MODELSYS
- 用verilog编写的运动自适应去隔行算法 表扩边缘检测 sad最小值编写-Verilog written with motion-adaptive deinterlacing algorithm detects the edge of the table to expand the minimum write sad
ChanEst_ise11
- OFDM基于导频的MMSE信道估计的Verilog完整工程，可以和matlab配合使用，源自清华电子系成熟的工程和算法-Verilog Project for MMSE ChanEst of OFDM
bch_verilog
- bch(255,239)编码算法的verilog实现，综合仿真通过，与matlab仿真的结果一致-bch(255,239)，using verilog
aes_core_128bits
- 高级加密算法verilog版,包括加密和解密算法，其中有s盒，行移位，列混淆等具体算法。-aes encryption for verilog，include subbyte,shiftrow,mixcol,addroundkey.
Motion_control
- 用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法-Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm
32-crc32
- 32位数据输入并行算法Verilog HDL代码。-32 bits of data input and parallel algorithm Verilog HDL code
Verilog-Design
- 复杂数字电路逻辑设计与实现，主要涉及算法的实现和具体的应用，很适合初学者入门-Logic design and implementation of complex digital circuits, mainly related to the implementation of the algorithm and the specific application, it is suitable for the beginner