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myCalendar
- 电子时间显示器现在在任何地方都有涉及到,例如电子表和商场的时间显示等等,所以它是一种既方便又实用的技术,而我们所做的万年历则是在它的基础上做出来的,通过万年历的制作,我们可以进一步了解计数器的使用,了解各个进制之间的转换,以及他的任意进制计数器的构成方法等,并且进一步了解74LS160的性质,以及门电路的使用等。-w jw jfw w lwjf e
counter10
- verilog编写的10进制计数器,并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
lqz3
- 这个程序是带置位的同步可逆(加1或减1)5进制计数器-This procedure is reversible with synchronous set (plus one or minus one) 5 binary counter
EDA-experimental-guide-book
- 利用QUARTUS II 8.1软件进行简单的EDA设计。该实验指导书原理阐述清楚,内容详尽,实验过程描述清楚,每一个实验步骤都有具体的截图。该实验指导书包括四个基本实验:实验1 QUARTUS II 8.1软件的使用;实验2 图形法设计24进制计数器;实验3 60进制计数器;实验4 简易数字钟。-Use QUARTUS II 8.1 software for simple EDA design. The experiment instructions Rationale clear, deta
CNT10
- 通过Quartus II 软件,VHDL语言实现10进制计数器-Achieve 10 binary counter
100hexadecimalcounter
- 用vhdl对GAL22V10进行编程,实现100进制计数器-Using VHDL programming on GAL22V10, 100 hexadecimal counter
counter60
- ise环境下用hdl语言编写的60进制计数器,已调试通过-60 binary counter
VHDL-code
- 使用VHDL语言进行门电路,优先编码器,译码器,各进制计数器,数码管显示的编写,在QUARTUS ii上模拟可用-Gates using VHDL language, priority encoder, decoder, each binary counter, write digital display, analogue available on QUARTUS ii
shuzizhong
- 数字钟,校时较分,显示,用元件例化写的vhdl文件,两个24进制,1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
DCNT60
- 60进制计数器设计仿真文件,已经经过仿真,程序及仿真结果无误。-60 binary counter design simulation files, has been the simulation program and simulation results are correct.
CNT10
- 用VHDL编写的10进制计数器,教学实例内容,在Quartus II 8.1下编译成功。-Using VHDL 10 binary counter, teaching examples content in Quartus II 8.1 compiled successfully.
EDA
- 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器(并行输入串行输出) 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器(6位右移寄存器) 19.二十四进制双向计数器 20.二选一 21
code
- 设计一个同步二十四进制计数器,理解触发器同步计数工作机制,掌握同步触 发控制的VHDL描述方法以及异步清零的描述方法。 -Design a synchronous binary counter twenty-four understanding count the trigger synchronization mechanism, master synchronous trigger VHDL descr iption method and asynchronous clear desc
myvhdl
- 用VHDL实现了简单的程序编写和仿真。是一个10进制计数器。-Using VHDL to make a simple 10 counter and it s simulation
sjnd
- EDA的29进制计数器,采用quartus完成,学校实验经常用-EDA s 29 binary counter, using quartus complete, the school often experiment
led_24_terminal
- 这是一段用VHDL语言写的24进制计数器,用数码管显示,我用了例化语句,分为24进制计数器模块,十位译码,个位译码,用cycloneII ep2系列实验板验证,能计数0~23。此程序还可以修改为100以内任何进制计数器。-This is a written in VHDL language 24 a binary counter, using digital tube display, I used the instantiated statements, divided into 24 hex
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
jishu99
- 100进制计数器程序,随着时钟自动计数并且在七段LED数码管上显示出来-100 binary counter, with the clock is automatically counted and displayed on the seven-segment LED digital tube
eda
- 一百进制计数器,以十进制计数器为模板增加十位计数,可类比写出多位计数器。九十九清零。-One hundred binary counter, decimal counter increased ten count as a template, you can write a number of analog counter. Ninety-nine cleared.
cnt63dis
- ISE环境下Verilog编程实现63进制计数器并用7段译码显像管显示-ISE Verilog programming environment under 63 binary counter with 7 segment decoder CRT display