搜索资源列表
OV7620_TEST
- FPGA驱动OV7620程序代码，SCCB部分由单片机完成，FPGA负责完成图像处理和TFT液晶的显示。经试验，效果不错！-FPGA-driven OV7620 code, SCCB completed in part by the microcontroller, FPGA responsible for the completion of image processing and TFT LCD display. The test, good results!
QAM
- 16qam调制器的FPGA实现。使用Verilog实现全数字16-QAM调制器。-16qam Modulator FPGA. Use Verilog for full digital 16-QAM modulator.
TLC549
- verilog TLC549AD采样程序 ，速度200K，在LED和数码管上显-verilog TLC549AD sampling procedures, the speed of 200K, in the LED and digital tube significantly
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
code
- 《无线通信FPGA设计》书里的matlab和verilog代码-the matlab and verilog code in 《Wireless Communications FPGA design》
基于FPGA的正弦信号发生器
- FPGA资料，正弦信号发生器，用verilog语言写的，内容详实
mouse
- 基于PS/2协议的鼠标驱动程序，用Verilog语言写成，可以用于任何型号的FPGA的驱动。-Based on PS/2 protocol mouse driver written using Verilog language can be used for any type of FPGA-driven.
learn_RS_coding
- 自己根据网上已有程序改写的(127,115)RS编码，有详细的注释及对FPGA实现算法的改写(参考try123.m)，希望可以让大家少走弯路-(127,115) rs encoder/decorder with detailed annotations.
USB2.0
- usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
1
- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
DDC_DUC
- 数字上下变频FPGA设计的详细介绍资料，还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
FPGA_PWM
- 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple
vga_control
- vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
counter
- 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
RS232_control
- verilog RS232信号解码模块。为在FPGA中的verilog代码。-verilog RS232 control module。
TS201_LINK_TRANSFER
- Ts201 link port verilog
sram
- SRAM控制器，含整个工程 vSRAM控制器，含整个工程 SRAM控制器，含整个工程-SRAM SRAMSRAMSRAMSRAMSRAMSRAMSRAMSRAM
fpga_ads8364
- fpga控制ti的多通道高精度ad芯片ads8364的verilog源码-fpga multi-channel high-precision control ti ad-chip ads8364 the verilog source code