搜索资源列表
div_3
- 不同方法FPGA/Verilog实现3分频,简单易懂，便于理解-Different methods of FPGA/Verilog realization of 3div frequency, easy-to-read, easy to understand
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
BeamformingFPGA
- 波束成型，基于FPGA的波束成型，包括两个文件，一个滤波器，一个xilinx仿真-Beamforming
FPGA_DDR_SDRAMverilog
- 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex-4，实现对DDRSDRAM的简单控制（对一系列地址的写入和读取）。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to wr
soc-gr0040-010309
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
lariviere2008uclinux
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
SerialPort
- 一个用verilog HDL 编写的串口发送程序，可以下载到FPGA中。已经在ActelFPGA中试过了，很好用。稍微修改之后，可以与Xilinx和Altera公司的FPGA兼容。-A programe dialogue to transmit a serial data which is writen by Verilog HDL.
alu
- 加法器FPGA 实现，精简，快速，高效，有仿真文件-adder base on FPGA ，verilog HDL
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
JIJIAQI
- Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
I2CVerilog
- I2C 控制器的 Verilog源程序, 适用于FPGA等应用领域-I2C controller Verilog source code,I2C controller Verilog source code
Tri-mode_Ethernet_MAC_Specifications
- document for mac 10 100 1000 ethernet verilog code.you find code in this site
FPGA2
- persian Tutorial for FPGA & verilog
verilog-8_1
- 基于fpga开发，使用初学者借鉴的一小段verilog程序代码，基于verilog的8选一-based on verilog，8——1
reed
- this the completedocumentation and code about reed solomon logic implemented on fpga in verilog.-this is the completedocumentation and code about reed solomon logic implemented on fpga in verilog.
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
MQdecoder
- Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA， Verilog HDL
undistort
- floating point arthematic function with verilog code
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
spartan_alu_8_bit
- Verilog based 8 bit ALU module, implemented on Spartan 3E FPGA.