搜索资源列表
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
hdb3_v3
- Quartus环境下使用Verilog编写的串口程序，RTL和时序仿真已过-Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed
uart_v1.1
- Quartus下开发Verilog编写的串口程序，主要包含串并互转模块等，通过RTL和时序仿真-Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed
HDLC
- Quartus下的HDLC编解码的开发，包含说明文档和设计报告，通过RTL和时序仿真-Quartus HDLC codec under development include design documentation and reports, by RTL and timing simulation
mips789.tar
- MIPS CPU RTL Reference Code
wisbone_2_ahb.tar
- ARM Bus Interface RTL Reference Code
iic
- 通过verilog语言实现了关于IIC协议，并且通过了modelsim的功能仿真验证以及板卡之间的RTL调试。-the verilog code about IIC standard，checked by modelsim，and make ture the IIC function in RTL。
t51.tar
- MCU 8051 Verilog RTL Code
uart16550.tar
- UART Verilog RTL Code
spimaster.tar
- SPI Interface Master Control RTL Verilog Code
spi_boot-rel_3_1_rev_C.tar
- SPI Boot Interface Control RTL Verilog Code
ALU32
- 32 bit ALU RTL Code using VHDL
2_digital_clock
- 采用Verilog HDL RTL 描述完成数字钟，基于basys3，软件平台：vivado-Using Verilog HDL RTL to complete the descr iption of digital clock based on basys3 software platform: vivado
remove_dc_input_tieoffs
- Design Compile综合RTL时，工具默认将tie 0的port优化掉，运用此脚本，可以将tie 0的port保持住。-When do synthesis, Design Compiler will optimize the tie 0 ports as default. This tool/scr ipt can keep the tie 0 ports in the output netlist.
rz_rtl
- Mini RTL for VisualStudio C/C-Mini RTL for VisualStudio C/Cpp
Joomla_1.5.23-joomlacn
- Joomla! 全球官方正式发布了 Joomla! 1.5.2 [Woi] ，Joomla简体中文汉化组也推出了相应的中文版本。这是一个维护性的版本，主要有： 1、支持非公历日期输出并去除日期对服务器本地化的依赖 2、TCPDF 支持RTL语言和GIF 3、改正了legacy模式下的缓存目录删除的问题 4、debug模式下，禁止页缓存 5、在Media Manager中提供了禁止Flash上传的功能 6、OpenID 功能行 BUG修复 7、增强了文章过滤功
spi_rtl
- spi的rtl级代码设计，内含spi_slave和spi_master的行为模型-Rtl level behavioral model of spi code design, and includes spi_slave of spi_master
openmsp430_latest.tar
- MSP430 RTL级源代码、代码目录结构说明，源代码说明文档等-MSP430 RTL open source,and the document about the source architecture and the source.
RS485_Revc
- rs485 receive end verilog rtl code
RTL-8188C-8192C-master
- miracast linux的源代码，功能已经实现，另付说明-miracast linux miracast linuxmiracast linux