搜索资源列表
rtl
- spi Flash控制器,适用于S25FL系列,欢迎下载-spi Flash controller for S25FL series, welcome to download
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现,包含详细GPIO定义文档,testbench,RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
ddr_controller
- 完整的DDR控制器设计,包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
S16C57
- 8位RISC CPU 设计IP,包含了文档、代码、仿真环境等-8BIT RISC MCU implemention reference ip,include rtl code,simulation and document
rsencoder.tar
- RS Encoder RTL verilog Code
ultimate_crc.tar
- Ultimate CRC Check RTL Verilog Code
arm7
- ARM7的RTL源代码,使用ARM7可以直接整合代码到源代码中。-ARM7 source code
cortex-M0_visio_RTL
- cortex-M0 visio版本的RTL电路图-cortex-M0 RTL visio
i2c_testbench
- i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
2cpu.tar
- Open core 的CPU RTL源代码,开放SOC的CPU;片上系统的源代码分析的CPU代码-Open core u7684CPU RTL u6E90 u4EE3 u7801 uFF0C u5F00 u653ESOC u7684CPU uFF1B u7247 u4E0A u7CFB u7EDF u7684 u6E90 u4EE3 u7801 u5206 u6790 u7684CPU u4EE3 u7801
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计,纯组合逻辑,对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分,可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码,以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
can
- can总线非常有用的资料,包括Can总线的RTL代码(files is very useful information of Can bus, RTL code is including in the files.)
src
- Digit serial adder, can be used in digital filter design You can choose the pipeline length, digit size and the word length of the adder.
PCIE DMA例子
- PCIE接口用例;32。64位BMD,非常全,非诚细致,验证过,调试过,可以用,不信你试试(used for dma pcie master include source rtl code)
SDR_using_MATLAB_Simulink
- Software defined Radio using matlab & simulink and the RTL-SDR
zedboard_master_XDC_RevC_D_v3
- 在这个实验中,使用Mathworks HDL Coder工具产生一个LMS噪声消除的滤波器。HDL coder会基于Simulink模型生成RTL模型封装进IP核。这个滤波器可以自适应地将未知的噪声滤除,输出处理后的信号。(In this exeriment, the Mathworks HDL Coder tool is used to generate a LMS noise elimination filter. HDL coder generates the RTL model base
rtl
- 实现sha1(128)杂散算法。输入为64bit,输出160bit。(Implementation of SHA1 (128) algorithm. The input is 64bit, and the output is 160bit.)
pci_host
- a pci host rtl code for reference.
usb
- verilog rtl code for usb controller.
codes
- Simple CPU design RTL.