搜索资源列表
60_binary_counter_vhdl_quartus2
- 一个60进制的计数器的VHDL源代码，测试可行。-a VHDL code of 60 binary counter and it test feasible.
counter
- 自己设计的一个小计数器。应用vhdl语言。-Their design a small counter. Application vhdl language.
CNT10
- 用VHDL编写的10进制计数器，教学实例内容，在Quartus II 8.1下编译成功。-Using VHDL 10 binary counter, teaching examples content in Quartus II 8.1 compiled successfully.
seg22
- 用VHDL语言编写，在cycloneii EP2C5T144C8N上实现计数器在数码管上的显示-Using VHDL language, on cycloneii EP2C5T144C8N achieve counter displayed on the digital control
gray_binary_conv
- 用VHDL实现的格雷码，有格雷码计数器、格雷码转二进制、二进制转格雷码！-VHDL implementation of the Gray code, there is Gray code counter, Gray code to binary, Gray code Binary!
CNT999
- 使用VHDL设计999加法计数器，并使用扫描译码电路将数字显示在数码管上。顶层设计使用的原理图-Design using VHDL adder 999 counters, and use the digital scan decode circuit in the digital tube display. Schematic top-level design using
state10
- VHDL 三、五奇数模计数器 占空比0.5-VHDL counter odd mode duty cycle 0.5
code
- 设计一个同步二十四进制计数器，理解触发器同步计数工作机制，掌握同步触 发控制的VHDL描述方法以及异步清零的描述方法。 -Design a synchronous binary counter twenty-four understanding count the trigger synchronization mechanism, master synchronous trigger VHDL descr iption method and asynchronous clear desc
lab4_solution
- ANVYL自带的例子，计数器设计，VHDL语言的。-ANVYL own example, counter design, VHDL language.
myvhdl
- 用VHDL实现了简单的程序编写和仿真。是一个10进制计数器。-Using VHDL to make a simple 10 counter and it s simulation
a
- 基于fpga的vhdl十进制 计数器，简单好用-Decimal counter vhdl fpga-based, easy to use
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.
CNT10
- vhdl设计的十进制计数器，仿真测试正确，可以使用。-decimal counter vhdl design, simulation tests correctly, can be used.
CNT4_S
- 该程序为运用VHDL语言，基于FPGA平台实现的一个四进制的计数器。-The program for the use of VHDL language, FPGA-based platforms to achieve a quaternary counter.
shiyan_4
- 这是一个VHDL写的计数器程序，仿真和硬件验证完全正确，是VHDL初学者学习的好例子。-This is a counter program written in VHDL, simulation and hardware verification entirely correct, is a good example VHDL for beginners to learn.
syn_cnter_4
- 四位计数器，VHDL版，基于cpld EPM570芯片-The four bit counter, VHDL version, EPM570 chip based on CPLD
led_24_terminal
- 这是一段用VHDL语言写的24进制计数器，用数码管显示，我用了例化语句，分为24进制计数器模块，十位译码，个位译码，用cycloneII ep2系列实验板验证，能计数0~23。此程序还可以修改为100以内任何进制计数器。-This is a written in VHDL language 24 a binary counter, using digital tube display, I used the instantiated statements, divided into 24 hex
Count10PVHDL
- 十进制计数器，用VHDL语言写的，编译环境是ISE13.4。里面有自己写的文档，简单介绍了一下流程，适合初学者。-Decimal counter, written in VHDL language, compile environment is ISE13.4.The inside have their own written document, introduced the process simple, suitable for beginners.
Limi
- 用VHDL设计一个6位二进制计数器：用VHDL设计一个6位二进制计数器-VHDL design with a 6-bit binary counter
SOC_Code
- 加法器，原码补码乘法器，ROM设计，PC计数器等的VHDL详细代码-The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail