搜索资源列表
RS
- 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
decoder_38
- 这是基于Quartus2 开发环境和verilog hdl语言写的38译码器-This is based development environment and Quartus2 verilog hdl language used to write decoder 38
encoder_83
- 这是基于Quartus 2开发环境和verilog hdl语音编译的83解码器-This is based on Quartus 2 development environment and compiler verilog hdl voice decoder 83
shumaguan
- verilog 写的，基于CPLD 的数码管实验，输入端是430单片机，cpld做了38译码器和8位所存-verilog written CPLD-based digital tube experiments, the input is 430 single, cpld made 38 decoder and 8 kept
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
Lab_02
- Verilog 3-to-8 Decoder on Spartan3E. Use 3 switches (SW[2:0]) as inputs. Keep SW[2] as MSB. Use 8 LEDs (LD[7:0]) as decoded outputs. i.e. if all input switches are turned off, LD0 should light up.
S1_38YIMA
- 38译码器，用ISE12.3实现。用Verilog HDL语言编写-38 decoder implemented with ISE12.3. Written in Verilog HDL language
yima
- Verilog语言描述38译码器功能，适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
3-8
- 基于verilog的3—8译码器，设计简单，程序清晰易懂-Based verilog 3-8 decoder design is simple, clear and understandable procedures
8bit_decoder
- Verilog code for 3*8 Decoder Circuit with testbench file-Verilog code for 3*8 Decoder Circuit with testbench file....
viterbideoderupdated
- Viterbi decoder source code is in verilog with CRCv-Viterbi decoder source code is in verilog with CRCv
reed_solomon_decoder
- Reed Solomon Decoder written in Verilog Libero core generator.-Reed Solomon Decoder written in Verilog Libero core generator.
serial-ports2
- verilog语言 12位串行数据传输转换为并行传输-12bit parallel to serial decoder and aynthesis result
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
des.tar
- DES Encoder and Decoder Verilog RTL Code
qiduanyimaqi_verilog
- 七段译码器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Seven segment decoder verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
HDB3-encoderauncoder
- HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现-HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
1553-EncoderDecoder---Documentation
- 1553b编解码参考设计 verilog 收发-1553b encoder decoder
Decoder_3X8
- Verilog code for 3X8 Decoder
BCH_dec_verilog
- BCH decoder based on Verilog design