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decoder-8b10b
- 可实现8b10b解码的verilog程序，经过测试-8b10b decoder，verilog
3-8-decoder
- 三八译码器,用Verilog HDL语言描述，包含文件说明以及波形截图-3-8 decoder using Verilog HDL language descr iption, including documentation and waveform capture
Three-eight-decoder
- 可以实现三八译码器功能的verilog代码-Can achieve thirty-eight verilog code decoder function
viterbi_soft
- (2,1,3)卷积码编码，软判决译码；matlab语言编码；verilog语言译码；-(2,1,3) convolutional code encoding, soft-decision decoding matlab coding verilog decoder
dvi-code-verilog
- dvi encoder and decoder for fpga
7duanyimaguan-Verilog-HDL
- 7段译码管的Verilog HDL程序，希望对大家有用-7 segment decoder tube Verilog HDL procedures
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
Decoder
- decoder 3 to 8 verilog
sanbayimaqi_verilog
- 三八译码器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Thirty-eight verilog decoder implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
manchester_encoder
- 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
viterbi-decoder-verilog
- viterbi verilog implemetation based matlab-viterbi verilog implemetation based matlab
verilog
- 用verilog设计的寄存器，储存器，锁存器，译码器以及在其中用到的八位串联并联间的相互转换。-Verilog design registers, memory, lock latch decoder and the use of eight series parallel conversion
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and
decoder
- 用verilog语言实现译码器,包含实验报告和数据流文件-Achieve decoder with verilog language, including reports and experimental data stream file
verilog
- VITERBI DECODER MODULE This module implements the FSM and instantiation of all the modules used for Viterbi decoding.
test1
- 七段译码器的verilog语言程序，功能由七根二极管来显示0到9数字的东西，就是显示器(seven-segment decoder)
top1
- 七段数码管译码器，可显示0~9共10个字符。(Seven segment digital decoder, 0~9 can display a total of 10 characters.)
encoder
- 基于1553B 模块 decoder 程序(decode_1553b_model.v)
3_8_decoder_20170407
- 一个简单的38译码器程序，内附真值表，在本实验例程程序中用于Cyclone 2。(A simple program for 38 decoder.)