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Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror
SPI_verilog_vhdl
- spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi
DualPortRAM
- 此程序是Verilog HDL语言读写RAM的程序希望大家有用-This is Verilog HDL Promang
PLL_50MHz_to_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序，50MHz分频为12MHz-Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency
VGA_char_ROM_success
- Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the cha
VerilogHDLPWM
- Verilog HDL编写的PWM，已运行-PWM Verilog HDL prepared
RTC
- actel fpga开发板fusion startkit实验例程，包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
VGA
- 应用VEROLOG HDL编写的VGA的IP核，可用于SOPC BUILDER中-the control of the i2c bus
8by8multiplier
- Verilog HDL for 8*8 multiplier-Verilog HDL for 8*8 multiplier..
verilog
- 利用verilog HDL编程驱动7段译码显示器，采用一位8进制方式，已在DE1开发板上得到验证。-Using verilog HDL programming display driver 7 of decoding, using an 8 hex mode, has been validated in DE1 Development Board.
Verilog74HCxxx
- 文档为用verilog编写的若干74hc系列器件的HDL实现。包括：74HC85、74HC74、74HC138、74HC151、74HC161、74HC194、74HC373、74HC283、74HC4017等-Documents prepared for the use of verilog series devices HDL certain 74hc implementation. Including: 74HC85, 74HC74, 74HC138, 74HC151, 74HC161,
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
RS232
- It s combination logic for UART. edited in verilog-HDL
RS232
- It s combination logic for UART. Edited in verilog-HDL.
Verilog-HDL-xiayuwen
- 夏宇闻老师的经典教程，对Verlag语言感兴趣的朋友或初学FPGA的朋友是个不错的教程。-XIA Wen classic tutorial teachers, the language of the Verlag FPGA beginner interested friends or friends is a good tutorial.
XilinxFPGA(1-60)
- 系统地讲述了Xilinx FPGA的开发知识，包括FPGA开发简介，Verilog HDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISEd开发环境使用指南等-Systematically describes the development of Xilinx FPGA knowledge, including Introduction to FPGA development, Verilog HDL language based on chip-based Xilinx HDL La
64B_adder
- Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
Verilog
- 着是一本主要介绍verilog HDL的书籍 希望对大家有用处-Is introduced with a verilog HDL books I hope to be useful
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
etd-0407109-183702-81-001[1]
- 文章介绍了YUV向RGB颜色空间转换的硬件电路实现算法.在高基乘法算法基础上,建立了参数化高基乘法算法模型,并给出了Verilog HDL描述 小数乘法的整数乘法近似和近似误差给予了详细的讨论.采用乘法单元复用的设计结果将在两个时钟周期内完成YUV向RGB的颜色空间转换.-This paper introduces the YUV to RGB color space conversion hardware algorithm. Matrix multiplication algorithm i