搜索资源列表
UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
RD1088_rev01.2
- FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
DW8051
- dw8051 verilog 源代码，包括cpu的各个模块定义，实现。可综合IP软核-dw8051 verilog
usb1_funct
- USB2.0的IP核（详细verilog源码和文档）-USB2.0 IP core (detailed Verilog source code and documentation)
fft
- altera公司fft ip核的运用。语言是verilog.-Altera company s fft ip. Language verilog.
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
brom_16x8
- 使用Verilog语言编写的ROM读写程序,使用IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-ROM using Verilog language literacy program, the use of IP core in Xilinx Spartan-6 run through, is a very good program Verlog
a
- 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写-verilog ise divider
Q
- 求模程序。。没有调用ip核，根据数学算法，逼近的思想，来编写的求模程序-verilog square
DDS
- FPGA产生DDS，未使用IP核，内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
lcd_controller
- verilog写的LCD的ip，avalonMM总线操作-verilog LCD ip, avalonMM bus operation
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE
FFTPVerilog
- FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
div
- FPGA的IP核中除法算法的源代码，是Verilog语言的，易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
cordic
- Altera 的CORDIC IP核，Verilog HDL-Altera CORDIC IP core, Verilog HDL
jpegencode_latest.tar
- fpga verilog 实现jpeg ip核编码器-fpga verilog forjpeg encode ipcore
wtut_ver.ZIP
- 码表程序，完整的verilog工程文件，完整的工程设计流程，包含时序约束，ip核的嵌入，以及DCM模块的使用-Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module