搜索资源列表
uart
- Verilog实现串口收发数据，包括整个quartus工程-Verilog serial port to send and receive data, including the whole quartus project
verilogsram
- FPGA开发板上的VerilogHDL编写的SRAM读写试验程序, 包括介绍文档, Verilog源码, 在Quartus II 8.1环境下测试通过-FPGA development board SRAM VerilogHDL prepared to read and write test procedures, including the descr iption document, Verilog source code, the Quartus II 8.1 environment te
Drive-ADS8365-state-machine
- 驱动ADS8365状态机,Quartus II Verilog-Drive ADS8365 state machine, Quartus II Verilog
mux4_to_1
- 四选一选择器的Verilog HDL编程，在Quartus II中实现了四选一数据选择器的功能。-Four elected a selector Verilog HDL programming, in the Quartus II in the four election data selector function
HDB3_decode
- 用Verilog HDL语言进行HDB3译码，并通过Quartus Ⅱ仿真验证-With the Verilog HDL language HDB3 decoding, and simulation by Quartus Ⅱ
FPGA_AD7822
- 基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl-A Design of the A/D Convertion Control Module Based on FPGA
mac控制器
- mac控制器ip核，语言verilog,开发环境xilinx ise,quartus ii等
UART
- 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
pic10_verilog
- 用verilog实现了PIC10系列单片机的IP核，代码基本来自一篇国外的文章《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》，对一部分进行了改进，主要包括对原文中有一些不可综合的@（posedge clk）语句的改写，使其能通过quartus的编译和综合，并且对跳转部分增加了比较多的注释，这篇文章写得非常好，感谢这篇文章的作者John Gulbrandsen先生，这篇文章让我学到了很多
HDB3
- 用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证-With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ
DE2_D5M
- 在Quartus ii 10.0的环境下，实现了从D5M摄像头中读取Bayer数据并转化为RGB，通过SDRAM缓存，VGA控制器，输出到显示屏的Verilog代码-In Quartus ii 10.0 Read Bayer format from D5M camera and convert to RGB format, through SDRAM, output on VGA port.
8-bitdecimalfrequency
- 学verilog时写的8位十进制频率计，开发环境为quartus II6.0.-When learning to write Verilog 8-bit decimal frequency, the development environment for quartus II6.0.
FPGAandSOPC
- FPGA&SOPC快速入门教程(PDF)，基于Verilog HDL语言，开发环境Quartus-FPGA
WAVE
- 关于波形发生功能的Verilog代码和Quartus文件完整文档。-Waveform occurred on the function of Verilog code and Quartus files a complete document.
uartnew
- 好用的UART通信源码，使用Verilog 编写 在QUARTUS下完成，并用ModelSim仿真通过-Source-to-use UART communications, the use of Verilog in Quartus to complete the preparation and use of ModelSim simulation through
memory_to_vector
- 这是一个Quartus的工程文件和verilog代码，讲如何把memory 变成vector-memory to vector
dk74191
- 基于quartus II软件 用verilog语言描述的74ls191-quartus II verilog 74ls191
aaa3_8
- 基于quartus II软件 用verilog 语言描述的38译码器-quartus II verilog
watch
- 基于quartus II软件 用verilog 语言描述的一个秒表-quartus II verilog
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog