搜索资源列表
dds
- 在quartus软件上，采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
dm9000a_init
- 在QUARTUS开发环境下的，verilog实现dm9000a的初始化-In QUARTUS development environment, verilog realize dm9000a initialization
vga_verilog
- 在DE1-SOC上运行的verilog HDL代码，可以驱动VGA显示彩条。quartus II 14.0可以直接使用-Verilog HDL code running on DE1-SOC, can drive VGA display color bars. quartus II 14.0 can be used directly
value_to_ascii
- 使用Verilog HDL 进行数值与字符ASCII码的转化，实现串口正确显示字符，编程环境Quartus -Use Verilog HDL to numerically with ASCII characters transformation, realize serial display character correctly, Quartus ii programming environment
nios_ruanhe_spi_3
- 这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。-This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their ow
New-Compressed-(zipped)-Folder-(4)
- verilog code for sequence detection implemented on FPGA using quartus simulator
taxi
- 使用verilog语言编写的出租车计价器，适用于Quartus II软件，使用Cyclone IV系列开发板测试可用。-Use verilog language taximeter for Quartus II software, using Cyclone IV series development board test available.
RS485
- FPGA/CPLD实现RS485通信协议，在Quartus ii平台上进行Verilog编程仿真-FPGA/CPLD realize RS485 communication protocol used to Verilog simulation on Quartus ii programming platform
heart-rate-meter
- 使用quartus II软件，verilog 语言，用来测试脉搏跳动次数，有单片机接口代码-Use quartus II software, verilog language, used to test the pulse beats, there are single-chip interface code
i2s_input
- 基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真-FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment
DA_TLC5620
- FPGA之TLC5620：将所给程序下载到实验箱，观察现象并结合现象理解程序的含义，使其实现单通道的DA转换：在按下通道的按键之后，用数码管显示输入的数字量，停止按键，数码管计数停止，继续按键则继续计数，按下复位键，则系统清零，数码管显示零值。此程序基于Quartus的编程环境，采用Veilog语言编写。-FPGA tlc5620: to the program downloaded to the box observed phenomenon and combined with the phe
qwe
- 基于quartus II verilog语言编程，实现有源蜂鸣器播放两只老虎 -Based on quartus ii verilog language programming, the realization of active buzzer playing two tigers
hdb3_v3
- Quartus环境下使用Verilog编写的串口程序，RTL和时序仿真已过-Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed
uart_v1.1
- Quartus下开发Verilog编写的串口程序，主要包含串并互转模块等，通过RTL和时序仿真-Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed
fft1024-verilogCODE
- fft 1024点verilog代码,适用于基-4的FFT算法描述，使用quartus，modelsim，-fftpoint 1024 verilog code
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序（已验证）Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
tugedafinal
- 使用Verilog HDL语言写的关于实现对ADC、MDC控制的程序，个人使用Quartus 7.2,在上面进行过仿真，暂时还没有发现问题-Using Verilog HDL language written on the realization of the ADC, MDC control procedures, personal use Quartus 7.2, in the above simulation carried out have had no problems found
vftvdr
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve
miaobiao
- 在Quartus II 环境下利用Verilog语言编写的秒表程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language stopwatch procedures, including modular devices and simulation waveforms
shizhong
- 在Quartus II 环境下利用Verilog语言编写的时钟程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language clock procedures, including modular devices and simulation waveforms