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cpu
- fpga实现了简单的cpu，有三个指令，有加法，减法，移动三条指令-fpga to achieve a simple cpu, there are three directives, there is addition, subtraction, move three orders
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
risc_cup
- 精简指令集CPU的VERILOG语言实现，很有用-RISC CPU the VERILOG language, very useful
IntelPInstruction
- 对intel的CPU指令进行详细解释。很全面-Intel' s CPU instructions on the detailed explanation. Very comprehensive
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
cpu
- 用Verilog语言编写的单周期cpu，实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu,
cpu
- 以ISE为平台设计的单时钟CPU，实现最基本的5条指令（R、LW、SW、BEQ、J） -ISE as a platform to design single-clock CPU, 5 to achieve the most basic instructions (R, LW, SW, BEQ, J)
10.12
- 为什么要有源代码？因为CPU可以理解的语言对人来说非常繁琐，以至于直接以CPU能够理解的语言编写程序几乎不可能。 另外不同的CPU能够理解的语言，即CPU指令是不同的，如果说一个程序员学习了针对某种CPU的编程语言，可是换一款CPU他又要重新学习的话，那么可想而知，几乎没有人能够胜任程序员的工作-Why have the source code? Because the CPU can understand the language of the people is very complic
CPU
- 这个CPU具有简单的指令集，我们可以使用简单的例子进行测试。为简单起见，我们只考虑CPU内部的关联，寄存器、存储器和指令集。那么我们就只考虑一下部分：读写寄存器，读写存储器和执行指令。-This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program. For simplicity, we will only consider the rela
simple-cpu-emulator(C)
- 含user_prog文件的解释型7条指令的简单CPU模拟器-simple cpu emulator for 7 insts
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
CPU
- 十指令简易CPU实现代码，可向外设端口读写数据-ten instruction simply cpu,it can write and read data to other equipment
Single-CPU-clock-cycle-
- 单时钟周期CPU的设计实验，能完成16条基本指令。-Single CPU clock cycle of experimental design，Article 16 to complete basic instructions。
CPU-project
- 硬件实验 设计一个给定指令系统的处理器 支持多条指令带进位和不带进位的ADD，SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,清零等等，内有设计报告-Hardware experiment，design a CPU with the command following:SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,clear, and so on.There is a disigning report in it.
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
cpu
- 实现了简单的精简指令集的CPU,里面带着原码-Create a Cpu of RISC
16-bit-CPU
- 单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书-Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions