搜索资源列表
ddr_ctrl
- verilog hdl coding DDR sdram control for fpga
DDR_SDRAM_controller_verilog
- DDR SRAM控制器的verilog完整设计文档(包含有完整的verilog源代码),
DDR_SDRAM_verilog
- DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的
DDR_FLASH_VHDL_Verilog
- FPGA DDR 外部RAM 读写的verilog代码,以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
upload_code
- 每个代码见压缩包内文件名,分别为使用单片机控制AD9627的代码,已在硬件电路实现;基于FPGA的DDR SDRAM控制源代码,将文件夹内文件加入同一工程即可;以及三份FPGA内部学习资料。 C代码开发环境为KeilC,verilog代码开发环境为Quartus。 -See each code within the compressed package file name, respectively, for the use of the AD9627 single-chip contr
xapp860
- 16通道DDR的LVDS接口(VHDL,Verilog and doc)-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
sdram_vhdl
- DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
DDDRR_SDRAM_cD
- DDR SRAM控制器的verilog完整设设计文档(包含有完整的verilog源代码), -DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
DDR_check
- altera公司cycloneII 2c35开发测试DDR的verilog代码,带仿真波形图。-altera cycloneII 2c35 verilog code development and testing DDR, with simulation waveform.
ddr_verilog
- DDR控制器的VERILOG代码;状态机;读写;刷新等操作-ddr controller,verilog
lpddr_verilog_model
- 美光 ddr sdram 仿真模型, 不可综合,用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
ddr_verilog
- verilog HDL语言实现在FPGA上控制DDR的逻辑,方法简单易懂,适合新手参考-Verilog HDL language on FPGA control DDR logical, simple to understand for novice reference
ddr_kongzhiqi
- fpga上用verilog HDL实现的ddr控制器,简单易懂,适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
ddr_sdr_latest.tar
- DDR 控制器 control verilog/vhdl 源代码 -ddr control source of verilog /vhdl
micron-lpddr-sdram-lpddr_model
- modelsim,micron公司的ddr sdram仿真模型,verilog。-modelsim,micron,ddr sdram simulat module,verilog。
altera_ddr_verilog
- altera的DDR控制器源码(包括仿真与说明文档),DDR为mt46v4m16,Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
lattice_ddr_verilog-for-orca4
- 莱迪思的DDR控制器源码(包括仿真与说明文档),DDR为MT46V16M8,Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
mt46v16m16p_ddr
- 官网下载的,经过板级验证的ddr control mt45v16m16p源代码,verilog语言设计,希望可以用到系统化设计。-Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design.