搜索资源列表
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
divider
- verilog 实现的除法运算器，可以进行修改。实现更多位宽的数据。-verilog implementation of division operation can be modified. Achieve more wide data.
Three-divider
- 用verilog硬件描述语言实现的三分频器-Three divider
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
divider
- verilog的除法器 有多重方法 很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
div_any
- 任意整数N分频器的verilog代码，N需要代码中进行设置-Any integer N divider verilog code N need to code set
divider
- 用verilog实现一个被除数位8位、除数为4位的高效除法器-Verilog to achieve a dividend of 8, division by four efficient divider
div5
- 用verilog描述的任意分频器，包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
verilog_fenpin
- verilog分频 verilog分频 verilog分频 -Divide Divide verilog verilog verilog verilog divider divider divider verilog verilog divider
verilog_fenpin0
- 这是一个verilog分频代码，代码比较简洁.-This is a divider verilog code, the code is relatively simple.
divider
- 位数可以任意修改的除法器，本人亲自测试，可以使用，效率和使用资源都是很少的-its a very good divider based on Verilog HDL
fenpin
- verilog语言编写的分频程序，可以通过defpram实现任意整数任意占空比分频，有详细注释-divider verilog language program can be achieved through defpram arbitrary integer divide any duty, detailed notes
divider_32bitdivby16bit
- verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
fen-pin-Verilog(2013-06-25-09.54.41)
- 任意小数分频，适用于对精确度要求不高的代码中-Any fractional divider, suitable for less demanding precision code
gen_divd
- FPGA分频器，verilog语言版本，通过实例化参数实现任意整数倍分频-FPGA divider, verilog language version, by instantiating an arbitrary integer multiple parameters Divide
clock_div
- verilog编写的分频器,基于计数器编写的-divider verilog prepared
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
SDivider16bit_V120
- 循环型除法器Verilog代码，带有8位小数，可使除法器固定长度，缩减时钟开销-Streamlined divider Verilog code, with eight decimal places, make fixed-length divider, reducing the overhead clock
counter
- 同步清零的可逆计数器，带时钟分频 Verilog HDL语言编写-Synchronous clear reversible counter with clock divider Verilog HDL language