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verilogdiv_3_5_7
- verilog写的奇数分频，适合初学的同学分析，容易上手，已测试。-verilog to write the odd divider, suitable for beginner students, easy to use, have been tested.
gray
- verilog语言编写的十分频器源码和测试文件-a program of ten divider,with a source and test file,using the verilog language
clock
- 利用verilog语言在fpga上实现不同分频器的设计，适合初学者学习-Verilog language in different divider on the fpga design, suitable for beginners to learn
div
- restoring divider in verilog
Clk_5
- 本文件为verilog所描述的基数分频技术，此实例为5分频电路。-This file is the verilog described base sub-band technology, this instance as a divider circuit.
verilog-HDL-Divider
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
Verilog_div_frequency
- 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频. -This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
modeldiv5
- 无分频电路，实现电路的五分频verilog代码，通过modelsim的仿真-No divider circuit circuit fifth frequency verilog code through modelsim simulation
led
- verilog编写的分频计数器，控制xilinx板子上led灯-verilog written divider counter control xilinx board led lights
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
clkdiv
- 任意分频电路的verilog实现，包含奇分频和偶分频-Arbitrary divider circuit verilog achieve, contains odd and even frequency divider
pll
- 用verilog实现奇数分频器程序，通过仿真验证-Odd divider program is verified by simulation with verilog
verilocode1
- verilog code1 of 32bit divider is uploaded
fp
- 用FPGA Verilog 语言编写的一个简单的分频器，内部有详细的中文注释，希望对初学者有益。-The FPGA Verilog language written in a simple divider, there are detailed notes in Chinese, hope useful for beginners.
Verilog1
- 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
vclkdiv
- 在QuartusII软件中用Verilog HDL编写的关于分频器的源代码-With in QuartusII software written in Verilog HDL source code of the divider
div_nonrestoring
- 用verilog 实现的除法器 ，被除数32位 除数为16位-Divider using verilog realize the dividend 32 divisor is 16
divider_VERILOG
- 采用VERILOG实现硬件除法器。提供RTL代码和仿真文件。-Achieved using VERILOG hardware divider. Provide RTL code and simulation files.