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dongmiaobiao55
- 基于FPGA的verilog语言描述和数码管显示时钟,并可以通过按键调节时间。-Clock verilog language to describe and FPGA-based digital tube display and buttons to adjust the time.
DS1302_demo
- DS1302实时时钟RTC的FPGA程序-DS1302 real-time clock RTC FPGA program
time_clock
- 时钟数码管显示FPGA例子-Verilog语言-Clock digital display FPGA example-Verilog language
chunge
- Xilinx FPGA verilog 数字钟-Xilinx FPGA verilog digital clock
Digital_clock11
- 基于FPGA芯片设计多功能数字钟,具有任意时刻定时闹钟,有分频器,计数器,等等模块构成-Regular alarm clock based on the FPGA chip design multifunction digital clock, any time, divider, counter modules
clock_hy
- 基于FPGA的闹钟制作,具有较时功能,整点报时,设定闹钟功能,查看闹钟功能。-FPGA-based alarm clock production than when the function, hourly chime, set the alarm clock function to see the alarm clock function.
1602lcdclock
- 使用vhdl语言在fpga平台上制作lcd电子钟,对于初学者,是一段很好的参考代码-Using VHDL language in fpga platform production LCD electronic clock, for beginners, is a very good reference code
bingzhuanchuan
- 用FPGA的状态及实现将单片机输出的16位数据串口输出 当数据输出完成后,LD数据线产生一个时钟的高电平-FPGA state when the the microcontroller output 16-bit data serial output data output is complete, the LD data lines generate a clock HIGH
fPGA_LED
- FPGA开发板做的一个简单LED驱动,使用Verilog语言实现- This is an example of a simple 32 bit up-counter called simple_counter.v It has a single clock input and a 32-bit output port module simple_count(input clock , output end of module counter
bin2chuan
- 在FPGA开发板上座的输出波形的实验,输出波形通过示波器显示出来-// This is an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_count(input clock , output reg [31:0] counter_out) always
Pll_prj
- FPGA中PLL模块的测试代码,代码通过例化一个PLL将25MHz系统时钟倍频到50MHz,然后通过两个不同频率时钟控制两个LED灯闪烁,通过闪烁频率可用观察PLL倍频效果-The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control
1602
- 用fpga实现1602计数器显示,因为我还没来得及做校准时间,所以只能称之为时钟计数器,不能成为电子钟。 网上很少用人公开这一类代码,一搜FPGA 1602,都是写一个静态的显示,在实际应用中,是没有用的,因此这个简单的例子,给大家抛砖引玉了! -Because I have not had time to do the calibration time, it can only be called a clock counter, can not become the elec
clock_lcd
- 基于FPGA用verilog实现电子时钟功能,适合初学verilog者-Suitable for beginners verilog verilog achieve FPGA-based electronic clock function
8.4
- 功能:基于VHDL语言,实现对ADC0809简单控制 --说明:ADC0809没有内部时钟,需外接10KHz~1290Hz的时钟信号,这里由FPGA的系 --统时钟(50MHz)经256分频得到clk1(195KHz)作为ADC0809转换工作时钟。 -: Based on the VHDL language, ADC0809 simple control- Descr iption: ADC0809 no internal clock, an external clock sign
digitalclock_demo
- 该程序适用于xilinx公司的FPGA开发板,spartan3E系列250型号 通过verilog编程实现数字钟的功能,下板子验证可用!-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
szz
- verilog HDL 硬件描述语言 FPGA 数字钟的实现 调整时间 闹钟等功能-verilog HDL hardware descr iption language implementations of FPGA digital clock adjustment time alarm clock functions
digital-clock_VHDL
- 使用VHDL实现数字时钟,已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA
uart_lcd
- 基于FPGA的UART通信,并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行,证明此程序稳定可靠。时钟为50MHz,语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company product
pailiezuhe
- 基于fpga的多功能数字钟,并且用1602显示,24小时,可调时,分,秒-Fpga-based multi-function digital clock, and with the 1602 show, 24 hours, adjustable hours, minutes, seconds
sine
- 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能,且数据ROM 在高速条件下,占用最少的逻辑资源,设计流程最便捷,波形数据获最方便。下图是此信号发生器结构图,顶层文件SINGT.VHD 在FPGA 中实现,包含2 个部分:ROM 的地址信号发生器,由5 位计数器担任,和正弦数据ROM,拒此,ROM由LPM_ROM模块构成能达到最优设计,LPM_ROM底层是FPGA中的EAB或ESB等。