搜索资源列表
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
CoreSPI_21_eval
- SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
LCD12864
- 基于 NIOS II的LCD12864 IP核设计，有了这个可以直接使用LCD12864-NIOS II of LCD12864 IP-based core design, with this can be used directly LCD12864
Quartus-IP---usage
- 关于IP核的应用的说明 很好的参考手册 不要错过-IP core applications on the instructions not to miss a good reference manual
mypro_synfifo
- 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
CPCI_PCIbus
- 为构建一个紧凑、灵活的 CPC I系统,在 IP核的基础上,采用 FPGA来实现 PCI总线接口电路。-To construct a compact and flex ible CPC I syste m, the PCI i nte rface c i rcuit i s i mp l em ented by FPGA based on IP core。
fft_ug
- altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FP
vga-ip-core
- vga ip core 资料 说明如定制一个ip核-vga ip core information such as a custom ip core
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
Whats-New-in-CORE-Generator-and-IP
- ise13.1中有什么新的ip核和资源，希望用ise的朋友能好好看看。-ise13.1 What' s new in the ip nuclear and resources in the hope that friends can have a good look at ise.
linux_transplantation
- 《S3C44B0开发板移植内核2.6 uclinux记录》以及一篇论文《基于Linux的USB 2.0 OTG IP核主机驱动的研究与实现》。-" S3C44B0 development board transplantation kernel 2.6 uclinux record" and a paper " Linux-based USB 2.0 OTG IP core host-driven research and implementation."
ug_altlvds
- 讲解lvds ip核的应用，altera lvds核讲解-altera lvds
i2c_master_slave_core_latest.tar
- IIC IP核，可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC，自定义II C IP核
ip_core
- 一些FPGA上用的到的IP核,种类非常全,开发小的ASIC基本上够用了-To use some of the FPGA IP cores, species are very full, the development of ASIC basically small enough
IP-code(8051-cpu-jtag-vga_lcd-i2c)
- ip核源码，包含8051,cpu,jtag,vga_lcd,i2c，使用vhdl语言编写，-ip nuclear source, including 8051, cpu, jtag, vga_lcd, i2c, using vhdl language,
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
spram
- 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
mc8051-IP
- VHDL 8051 IP, VHDL写的8051的IP核。-VHDL 8051 IP
AES-IP-core-key-expansion-module
- AES IP核密钥扩展模块设计与仿真（设计过程及程序，测试程序）-AES IP core key expansion module design and simulation (the design process and procedures, test procedures)