搜索资源列表
sim
- i2c代码及modelsim仿真,可以读写eeprom。-i2c code and modelsim simulation, can read and write eeprom.
PtDdcCic3
- CIC三级抽取滤波器源代码,包括modelsim的仿真代码,已经测试过稳定性-cic 3 cascade filter source code, including modelsim simulation code, and test
CPU
- 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构,实现了cpu的基本功能如:加减乘除运算,跳转等。此外,里面有一个17位的ROM区,是存储指令的。你可以写出一段17位的指令代码,并放入ROM区,该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan
umv_demo
- UVM实践指南的第一章的例程代码 在win7 modelsim SE 10.0c完美运行。。。。。欢迎下载测试,有疑问联系我-The first chapter of the routine practice guidelines UVM code runs perfectly in win7 modelsim SE 10.0c. . . . . Welcome to download the test, have questions, contact me
QPSK
- 这是关于QPSK调制解调的VerilogHDL语言的代码,还有用Modelsim仿真的工程文件。testbench都已经写好了。-This is the QPSK modulation and demodulation of VerilogHDL language code, as well as with Modelsim simulation project file. testbench have been written.
CORDIC
- CORDIC的FPGA代码和modelsim仿真,亲测可用,精度较高-CORDIC FPGA code and modelsim simulation, pro-test available, high precision
fft1024-verilogCODE
- fft 1024点verilog代码,适用于基-4的FFT算法描述,使用quartus,modelsim,-fftpoint 1024 verilog code
fadder4
- 例化语句生成的四位全加器代码,写在word里了,也有MODELSIM测试代码-Four cases of full adder codes generated by the statement, written in the word again, and there MODELSIM test code
simProcessorEx
- 一个简单微处理器内核的VHDL程序,包含源代码(位于Source目录内)及ModelSim仿真代码(位于testBench目录内)。使用该内核进行一个功能验证程序(位于simProc_test目录内)-a simple processor core program and test code based on VHDL language
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
ethernet
- opencore上实现以太网mac层的开发版Verilog代码,含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
cui_mcu
- 微处理器设计(verilog)带测试验证代码modelsim仿真无误 -Microprocessor design (verilog) with modelsim simulation test verification code is correct
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译,并使用modelsim进行了验证,内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
spi_verilog
- spi通信协议的设计参考,对于初学者可以以此为参考进行设计,代码可在仿真软件中验证(modelsim、VCS等)。-Spi communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
uart_model_verilog
- uart通信协议的设计参考,对于初学者可以以此为参考进行设计,代码可在仿真软件中验证(modelsim、VCS等)。-Uart communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
dma_bridge_verilog
- DMA控制模块的设计参考,对于初学者可以以此为参考进行设计,代码可在仿真软件中验证(modelsim、VCS等)。-DMA control module design reference, for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
usb_host_device_verilog
- USB-host-device控制模块的设计参考,对于初学者可以以此为参考进行设计,代码可在仿真软件中验证(modelsim、VCS等)。-USB-host-device control module design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
DDR2_Control
- 本源码是用FPGA控制DDR2芯片的vhdl源码,并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code
my_emac
- modelsim仿真网口MAC收发数据包的实现代码-Modelsim simulation port MAC transceiver packet implementation code
ultrasonic
- 基于xilinx的超声波测距代码,通过了modelsim的仿真实现-Based on xilinx ultrasonic distance code, through the modelsim simulation to achieve