搜索资源列表
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.
easy_to_modelsim
- 这里包含6个modelsim的学习资料,包括了经典教程、答疑和分别针对VHDL、Verilog语言的仿真例程。-This contains six modelsim of learning materials, including the classic tutorial, tutorials, and were aimed at VHDL, Verilog simulation language routines.
modesim
- 讲述使用modelsim进行验证,使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档,对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc
74hc4017
- 实现的是扭环形十进制计数器,用verilog HDL 语言,在Actel公司提供的LiberoFPGA开发环境下实现,代码经过验证,可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in t
div_any_nodd
- 使用verilog硬件语言实现任意奇数分频,使用ise11.1和modelsim仿真测试-Verilog language using any odd hardware divide, and the modelsim simulation testing using ise11.1
div_n_0_5
- 使用verilog实现任意奇数n+0.5分频,使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
ModelSim_chinese
- ModelSim全套中文手册 东西还挺全的 个人觉得对初学者而言还是挺有必要看看的-Getting Started tutorial Amy FPGA series of experiments a number of entry-e-studio programs verilog
modelsim6.0
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。-Mentor' s ModelSim is the industry' s best HDL language simulation software, it can provide a friendly simulation environment, the industry' s only single-kernel
risc8
- 基于verilog的8位risc-cpu源码,modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
1024Mb_ddr2
- DDR2的Verilog仿真代码,可以使用ModelSim仿真-DDR2' s Verilog simulation code, you can use the ModelSim simulation
modelsimtest
- 里面是一些verilog代码和一些modelsim的教程-There are some verilog code and tutorials modelsim
sdr
- 全数字OQPSK解调算法的研究及FPGA实现 论文介绍了OQPSK全数字接收解调原理和基于 软件无线电设计思想的全数字接收机的基本结构,详细阐述了当今OQPSK数字 解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法, 并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的 仿真和性能分析,确定了FPGA中的系统实现方案。在此基础上,本文采用Verilog HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计
viterbi219
- 2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过--(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform
convcode
- 基于Modelsim的卷积码(2,1,7)的Verilog实现,采用直接生成-Modelsim-based convolution code (2,1,7) and Verilog implementation of direct generation
add4
- 四位加法器verilog源代码,经过modelsim仿真验证正确,用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
SdpCtrlSimPrj
- 一个对芯片进行软件解锁的仿真工程,可以在Modelsim环境下仿真运行,可作为学习Verilog和仿真的朋友的一个很好的例子-One pair of chip engineering simulation software unlock, you can run in Modelsim simulation environment, simulation can be used as learning Verilog and friends a good example
test_verilog
- verilog编程实践,内含多个实例,均已在modelsim下编译通过-a simulation
iic
- 我自己写的verilog ,实现iic总线的协议,分为带存储和不带存储两种。内部有测试代码程序,用modelsim仿真通过的。谢谢大家。-I write verilog, to achieve iic bus protocol is divided into storage and without storage with two. Thank you.
verilog_Common_arithmetic
- 常用逻辑运算,加法器,乘法器及除法器的verilog语言,可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
dtrigger
- 常用触发器——D触发器的VERILOG语言描述,可用Quartus II 9.0 和modelsim环境实现。-Common triggers- D flip-flop of VERILOG language descr iption available Quartus II 9.0 and modelsim environment to achieve