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code_lock_vhdl
- 在ISE环境下用vhdl写的一个密码锁程序。下载到xilinx 公司的 spartan6 的板子上验证过的，也有仿真代码。主要就是几个状态之间的转换，用了一个moore状态机。-In the ISE environment using vhdl to write a lock program. Downloaded to the board spartan6 xilinx' s proven, there are simulation code. Mainly the conversion
Moor-ANSI-S3.4-2005
- Moore响度计算的Matlab程序，已经按美标附件检验方法验证其计算精度-Moore loudness calculation with matlab
MOORE_inverse_C
- 利用C语言实现MOORE-PENROSE广义逆矩阵的计算，经试验OK。-The realization of MOORE-PENROSE generalized inverse matrix is calculated by using the C language, through the test of OK.
ts_bm
- Boyer-Moore text search implementation for Linux v2.13.6.
77
- 基础实验_12_有限状态机 ：Moore型序列检测器-Basic experiment _12_ finite state machine: Moore type sequence detector
berkley-07-SeqLogicIIIx2
- Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines-Models for representing
moore_contour_code
- This code is an example of the Moore neighborhood contour algorithm using MATLAB
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
moore
- 一个简单的检测101序列的摩尔型状态机，里面包括了testbench的源代码。-A simple detection of 101 sequences of the mole state machine, which includes the testbench source code.
Ver_prog
- Verilog programs for trafficlight controller, dicegame, mealy,moore machines and universal shift register
FastInString
- Replace the InStr function in Visual Basic 6 with this new faster function with Boyer-Moore Algorithm
fpga_ztj
- 对于FPGA状态机的设计心得 对于FPGA状态机的设计分为两类，分为mealy状态机和Moore状态机，mealy状态机的输出不仅与当前输入有关还与当前状态有关，而Moore状态机的输出仅与当前状态有关。对于状态机描述首先要知道输入，输出，当前状态，下一个状态的基本定义。 对不状态机的设计，首先要有一个初始状态，一般命名为IDLE，其状态一般设定在复位信号到来时。 对于时钟敏感的信号，在其最大的一个时钟周期作为总的状态循环，最下的一个时钟信号最为一个状态指令，一般用于时序图的描述；对
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
MSc---Hardware-JPEG-Decompression
- Due to the ever increasing popularity of mobile devices, and the growing number of pixels in digital photography, there becomes a strain on viewing one s own photos. Similar to Desktop PCs, a common trend occurring in the mobile market to com-
traffic_control1
- （1） 学习和掌握了解分频电路、通用同步计数器、异步计数器的使用方法； （2） 理解Moore和Mealy两种状态机的一般编程方法，能够按工程控制需求设计相应的逻辑和时序控制程序。 以开发板上的六盏LED小灯模拟，三盏小灯模拟一个方向的红黄绿交通灯灯，用VHDL语言编程实现红绿交通灯控制程序。 -(1) to learn and master the understanding of frequency division circuit, universal synchronous
FPGA-Traffic-Light-Controller
- （1） 学习和掌握了解分频电路、通用同步计数器、异步计数器的使用方法； （2） 理解Moore和Mealy两种状态机的一般编程方法，能够按工程控制需求设计相应的逻辑和时序控制程序。 以开发板上的六盏LED小灯模拟，三盏小灯模拟一个方向的红黄绿交通灯灯，用VHDL语言编程实现红绿交通灯控制程序。 -(1) to learn and master the understanding of frequency division circuit, universal synchronous
soda_machine_mealyamoore
- soda_machine的一个有限状态机，用verilog描述，分别有moore和mealy,还提供了testbench.-soda_machine of a finite state machine, with verilog descr iption, respectively, moore and mealy, also provides a testbench.
boundray-tracing
- 用matlab实现边界追踪，包括Moore和Freeman Chain Code表示提取的边界-Boundary tracking with matlab, including Moore and Freeman Chain Code to represent the extracted boundaries
pca
- fusion d'image satilittaire