搜索资源列表
DoubleDort_RAM
- 双口RAM控制时序仿真 双口RAM控制时序仿真 -Control of dual-port RAM dual-port RAM timing simulation control timing simulation to control dual-port RAM Timing Simulation
VHDL2
- 序列信号发生器: 在系统时钟的作用下能够循环产生一组或多组序列信号的时序电路,(循环产生一组序列信号0111010011011010) 序列检测器: 检测一组或多组又二进制码组成的脉冲序列信号,当序列检测器连续收到一组或多组序列信号,如果与预先设置的码11010相同的时候,输出1,否则输出0. -Sequence of signal generator: the role of the system clock cycle to generate one or more si
vga
- vga显示时序控制,vhdl产生所必需的时序-vga display timing
avr16-step_motor-control
- 本设计采用ATEML公司的mega16 单片机对步进电机进行控制,通过IO口输出的具有时序的方波作为步进电机的控制信号,信号经过芯片L298N驱动步进电机;同时,用键盘来对电机的状态进行控制。-This design uses the company ATEML S mega16 SCM ATEML stepper motor control, through the IO port output with the timing of the square wave as a stepper m
netctoss
- 该项目是为电信运营的IP计费服务的。主要为openlab在线实验室出租业务。该 系统运行于Sun Solaris Unix系统,数据库采用Oracle9i ,Web部分采用Weblogic 服务器。后台主要由数据采集系统从AAA服务器采定时采集出用户的登入登出信息, 存入数据库相应的表中,由数据整合系统定时对采集的数据按时、天、月、年进行 整合,以便对web部分的查询提供支持。前台部分主要分为用户自服务管理,资费 管理,用户管理,管理员管理,帐单管理,帐务
SDRAM_CONTROLlER_Modelsim
- SDRAM控制器,Verilog代码编写,让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和文档-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
adc_verilog
- 用verilog编写的ADC控制接口,只需根据具体ADC器件的时序图修改代码就可运行。-ADC prepared with verilog control interface, just depending on the ADC timing diagram of the device can modify the code to run.
132467653432
- SLE4442中文技术手册,详细的介绍了sle4442的控制方式。包括详细的时序图。-SLE4442 Chinese technical manuals, detailed introduction to the sle4442 control mode. Including a detailed timing diagram.
SearchEngine
- 搜索引擎模块是一个很主要且常见的功能。一个好的搜索引擎能给用户使用带来方便。在“站内”选项卡下的搜索框中输入欲查询的关键词,如“PHP 字符串,处理技术!”,单击“极速搜索”按钮,系统会首先过滤欲查询关键词的标点符号,然后对过滤标点符号的关键词进行分词操作,接下来在数据库中检索与之匹配的信息资源。同时实现搜索计时及查询结果汇总功能,并在结果集中高亮显示查询关键词,最后以分页形式输出匹配结果给用户。-Search engine module is one of the main and commo
24c512
- 关于大容量24C512的读写程序,很全,包括了全部的时序程序,可以值复制各个函数去使用!-24C512 on reading and writing large programs, it is full, including all of the timing procedure, you can copy the value of each function to use!
ECGSYNC-physionet
- ECGSYN generates a synthesized ECG signal with user-settable mean heart rate, number of beats, sampling frequency, waveform morphology (P, Q, R, S, and T timing, amplitude,and duration), standard deviation of the RR interval, and LF/HF ratio (a measu
datachooser
- Java Swing 日期控件 增加时间选择功能-Java Swing Date timing control function to increase
i2c
- 标准I2c读写时序,verilog Hdl-Standard I2c read and write timing, verilog Hdl
dac0832
- 关于CPLD程序,采用VHDL语言实现DAC0832的时序控制-CPLD about procedures, the use of VHDL language implementation of the DAC0832 Timing Control
IBM-CLOCK
- 基于8086架构,调用系统14H号中断实现时序的电子钟。-Based on the 8086 structure, call the system 14H interrupt electronic clock timing.
74HC164
- 芯片并出8位芯片74ls164的使用程序,按工作时序编写。-Chip and out of the use of 8-bit chips 74ls164 procedures, timing of work to prepare.
74hc165
- 51单片机,仿真,74hc165 时序控制,并入传出芯片,本人自编,绝无仅有,指针调用.-51 SCM, simulation, 74hc165 timing control, came into the chip, I wrote, unique, pointer calls.
ARM-Cortex-M3-alarm
- 基于ARM-Cortex M3的闹钟。。。。具有定时闪烁,蜂鸣器等功能。使用cortex c编写-Based on the ARM-Cortex M3 alarm clock. . . . Timing flashes, the buzzer function. Written in the cortex c
AT24C04
- AT24C04采用IIC串口总线方式进行数据传送,读写数据的时序源代码!-AT24C04 way with IIC serial bus data transfer, read and write data timing source code!
pcirw
- quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序,可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,bla