搜索资源列表
CY7C68013.rar
- USB2.0的Verilog实现，含有完整的FPGA代码,Use Verilog to implement the USB2.0 protcol
config_ad9957
- 用Verilog正确配置ad9957，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad9957,, compiled in the ISE environment and realization of the right
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
arbiter.rar
- 一个用verilog编写的总线仲裁程序。多个设备共享总线，不同设备的优先级是变化的，保证每个设备都有公平的使用总线的机会。,Verilog prepared a bus with arbitration proceedings. Multiple devices share the bus, the priority of different devices is changing to ensure that each device will have a fair opportunity t
butterworth_iir_verilog.rar
- 基于butterworth的iir滤波器的verilog代码，已经通过测试。,err
8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
fft_verilog.rar
- FFT IP core 源码 状态控制机,FFT IP core
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
CRC32.zip
- VHDL CRC32 VHDL CRC32,VHDL CRC32 VHDL CRC32
Audio_Codec_WM8731.rar
- 这是一个控制WM8731的IP。通过SOPC直接可以挂在总线下。,This is a the WM8731 control IP. Can be linked through the SOPC directly under the bus.
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
pid_controler_latest.tar
- PID控制器的verilog实现，做闭环控制器的人可以参考-PID controller verilog implementation of closed-loop controller may make reference to
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
TLC2543
- 使用Verilog实现的AD采样，很有用的！-Implemented using Verilog AD sampling, very useful!
DA
- FPGA控制DAC2807的源文件，Verilog。附有简单文档-FPGA control DAC2807 source, Verilog. A simple document
EnDatlightversion
- 海德汉绝对值编码器的ENDAT2.2协议代码，用于编码器数据的解码，然后把得到的数据传送给DSP处理，我们公司用于高精度伺服驱动器上。-Heidenhain encoder absolute agreement ENDAT2.2 code encoder data for decoding the data and then transmitted to the DSP processing, our company for high-precision servo drive.
Omnivision SCCB interface verilog model
- Omnivision SCCB interface verilog model
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
sata_device_model
- sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help