搜索资源列表
Verilog_for_BCH
- 使用verilog语言实现BCH编码，用于通信信道编码-Using verilog language implementation BCH coding, channel coding for communication
50M
- verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
fifo-verilog
- 自己设计的一种FIFO寄存器，用verilog 编写，QUARTUS II下验证-Own design of a FIFO register, with verilog preparation, QUARTUS II certification under
handshake
- AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
I2C_Slave
- I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
OR1200_verilog
- or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog descr iption of the risc cpu realize, cpu source code analysis and chip design source book
IEEE_Verilog_2001
- Verilog 2001 编程规范，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
ad_test
- ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现-ad9777 test procedures, the SPI is initialized, the use of ISE environment, the successful realization of comprehensive and
1602
- verilog HDL语言编写的完整工程，功能是点亮1602lcd，在lcd上显示英文和数字-verilog HDL languages complete works, the functions of light 1602lcd, in the lcd display in English and the number of
SPI_controller
- SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
delay_line
- 延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module
MAX_II_using_the_example_of_the_UFM_block
- BJ-EPM240V2实验例程以及说明文档实验之十四MAX II的UFM模块使用实例-BJ-EPM240V2 experimental test routines as well as documentation of the MAX II 14 UFM module uses examples
CORDIC_SINE
- xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
SPI
- Verilog SPI 源码（来自网络）-Verilog SPI
Sequence-detector-design
- 序列检测器设计的思路大多都是用FSM来实现的,此思路是通过移位寄存器来实现序列检测-Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
rrc_filter
- this is a verilog code for root raised cosine filter
digitalclock
- Verilog数字时钟 实现24小时的监控，用七段码显示出来，包含时序图等 在ISE下仿真-digital clock Verilog