搜索资源列表
CMI
- 基于FPGA/CPLD的CMI编解码设计，含程序说明及仿真截图。-Based on FPGA/CPLD' s CMI codec design, including descr iption of the procedures and simulation screenshot.
OV7620
- 这是我自己编写的FX2控制ov7620的VERILOG程序，网上很难找的-This is my own written FX2 control ov7620 the VERILOG program, very difficult to find online
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
rgb2yuv
- 用VHDL和verilog编写的RGB颜色空间到YUV颜色空间的转换程序, 是FPGA视频处理中的常用程序!-Written in VHDL and verilog using RGB color space to YUV color space conversion process is commonly used in video processing FPGA program!
iic_master
- it is a iic source verilog code with its testcase which can act only as master
spi_verilog
- SPI协议Verilog HDL程序，内含testbench 文件
YUV2RGB
- 关于YUV转RGB的verilog源代码、说明文档和modelsin仿真，相信对大家一定有很大的帮助，我费了好长时间才找到的！-YUV to RGB on the verilog source code, documentation and modelsin simulation, we believe that there will be a great help, I spent a good long time to find it!
NAND_Flash_Controller
- FPGA实现的NandFlash控制器（带ECC）文档+源代码。-FPGA implementation NandFlash controller (with ECC) document+ source code.
CRC_32
- 用verilog语言实现的的的32位CRC生成与检验的代码-The 32bits CRC using hardware describe language of verilog
GMSK
- GMSK的FPGA实现程序，全数字GMSK实现方案。-GMSK FPGA-implementation process, all-digital GMSK implementations.
temperature
- 使用FPGA控制18B20达到温度采集过程，并显示在数码管上。-Achieved using the FPGA control 18B20 temperature acquisition process and display the digital pipe.
flash
- fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
i2s_rel1_2
- I2S verilog HDL code including test environment
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
QAM16_Souce_code
- QAM 16 源代码，用于无线通信中或者广播中的调制。-QAM 16 source code, used in wireless communication or broadcasting.
Altera_Verilog_Coding_Style
- Altera公司的Verilog编程风格 Altera_Verilog_Coding_Style-Altera' s Verilog programming style Altera_Verilog_Coding_Style
MIT_Video-Scaler
- MIT的video scaler论文，文章后面附有c和verilog程序源代码，分为水平缩放和垂直缩放-MIT video scaler papers, articles, source code attached to the back, divided into horizontal scaling and vertical scaling
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal