搜索资源列表
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
pci_t
- verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
DW8051_HDL
- DW8051 Verilog VHDL 源码和文档 -DW8051 Verilog VHDL Code and document
74HammingCode
- 用VHDL语言编写的可以实现（7，4）汉明码编解码的程序。-Using VHDL language can be achieved (7,4) Hamming Code Codec procedures.
sha256_512
- Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.
prbsforip
- 本文设计了一种简捷而又高效的伪随机序列产生方法，最后通过统计对比，说名这种方法产生的随机序列不仅周期长 还具有两好的随机特性-This paper designed a simple and efficient method for the selection of pseudo-random sequence, and finally through statistical comparison, saying that this method of random sequence gen
test_uart
- uart VHDL code : include tx,rx,parity bit control
ide_control
- 三段式Verilog的IDE程序，但只有DMA部分，需要自己添加PIO的代码-Verilog three-step procedure of the IDE, but only parts of DMA, PIO required to add their own code
1234
- 一段NOR FLASH 控制器的Verilog源码-Verilog
hdl
- 网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。-a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.
Turbo
- 基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
adder8
- Vrilog HDL 八位加法器源程序-8 adder Vrilog HDL source
PCM
- 基于FPGA的PCM编码器与解码器的设计-about fpga and pcm
stopwatch
- VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
lai_PWM
- FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
rs_enc
- Verilog code for RS-(255,239) encoder.
DPD_LUT
- 一种基于LUT的预失真方法。其中的一部分，有参考价值。-one method of DPD based on LUT
16QAM
- 关于16-QAM调制系统的FPGA实现的论文-16-QAM modulation on the FPGA system to achieve the papers
alu
- 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware desc
PIC-Code
- the verilog code used to design a PIC uC