搜索资源列表
mydesign1
- 用verilog实现求最大公因数的程序,包括完整的工程-Verilog seeking to achieve with the largest common factor of the process, including the complete works
led_water
- Altera FPGA流水灯工程文件Verilog语言代码,作为入门级的参考程序-Altera FPGA Verilog flow light project files language code, as the entry-level reference program
RTC
- actel fpga开发板fusion startkit实验例程,包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
lab_simulation
- verilog 开发的,模拟CPU流水线操作的工程设计。-verilog developed to simulate the engineering design of CPU pipelining.
reset
- 这是个关于同步复位和异步复位问题的探讨,最后得出同步释放,异步复位的效果最好 文件中有编好的verilog文件工程,以及仿真结果和RTL分析图,分析的很详细-This is a synchronous reset and asynchronous reset on the issue of the conclusion that synchronous release, asynchronous reset of the best documents are programmed veril
cla16
- 16位超前进位加法器的源代码,整个工程文件都有,是在ISE10.1下建立的,可以帮助理解超前进位原理(对了,是Verilog的,因为上面没看到只好选VHDL了)-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
Verilog_USB_OUT
- USB out,使用Verilog写的,包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document,USB firmware
Verilog_USB_IN
- USB in 模型,作为输入,包括基于Altera的工程、源码、固件,使用Verilog-USB in model, as input, including the Altera-based project, source code, firmware, Verilog
Modelsim--script-usage
- modelsim是Mentor graphics公司推出的HDL代码仿真工具,也是业界最流行的HDL仿真工具之一。支持图形界面操作和脚本操作。常见的图形界面操作相对直观,但是由于重复性操作几率高、处理效率低、工程的非保存性,对于大规模的代码仿真不推荐使用;脚本操作完全可以克服以上的缺点,把常见的命令,比如库文件和RTL加载、仿真、波形显示等命令编辑成.do脚本文件,只需要让Modelsim运行.do文件即可以完成仿真,智能化程度高。本文重点介绍Modelsim常见命令的使用,以及如何使用.do
Magic-Gloves-master
- 魔法手套主工程文件VERILOG语言,蛮不错的-Magic glove main project file VERILOG language, pretty good! ! !
20104169105873879
- 主要功能:pci9054芯片本地总线控制示例程序,可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断,产生1,2,3等递增数据,配合pci9054驱动和应用程序完成数据传输 2.说明:文件夹内是Quartus 9.0的工程文件,使用Verilog语言,使用器件是Cyclone2,应用于其他FPGA时,直接调整管脚即可。-Main features: pci9054 local bus control chip sample program can be used for pci driv
i2c
- I2C接口程序,整个工程文件,文人已仿真,下载,在FPGA上测试成功 verilo语言-I2C interface programme,the whole project file,I have simulated and tested in FPGA successfully .verilog language.
Example-8-2
- Verilog延时建模设计 Example-8-2目录下为设计工程子目录,目录中包含以下内容。 1. Blocking_LHS_Delay:阻塞赋值左式延时。 2. Blocking_RHS_Delay:阻塞赋值右式延时。 3. NonBlocking_LHS_Delay:非阻塞赋值左式延时。 4. NonBlocking_RHS_Delay:非阻塞赋值右式延时。 -Delay Modeling Verilog Design Example-8-2 design engi
jkdff
- 本工程为jk触发器的verilog语言程序工程,安全有效,可独立使用,可作为一个独立的模块。-This project is jk flip-flop verilog language program works, is safe and effective, can be used independently as a separate module.
Nios_Example_07_SD_35TFT
- 这是一个nios工程,控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的,MCU软核程序有C语言编写。通过这一个完成的工程,你就会明白SOPC的一些实现方法。-This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written
add4
- 四位加法器verilog源代码,经过modelsim仿真验证正确,用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
SdpCtrlSimPrj
- 一个对芯片进行软件解锁的仿真工程,可以在Modelsim环境下仿真运行,可作为学习Verilog和仿真的朋友的一个很好的例子-One pair of chip engineering simulation software unlock, you can run in Modelsim simulation environment, simulation can be used as learning Verilog and friends a good example
ads8132_verilog
- 关于ADS8132的硬件语言verilog HDL描述,精简实用,而且准确,已通过工程验证-About ADS8132 verilog HDL hardware descr iption language, streamlined and practical, and accurate, has been verified by the project
zhuan
- 一个关于串并和并串转换的verilog的工程,代码简洁易懂-this is a sample program project for transformation
pwm4
- 用verilog编写的脉冲宽度调制器的FPGA工程-With verilog write pulse width modulator FPGA project