搜索资源列表
VGA
- quartus ii verilog hdl 实现VGA时序及显示的工程和源程序 -quartus ii verilog hdl vga timing project and source code
PCF8563
- quartus ii 实时时钟pcf8563工程及源码 Verilog hdl 实现iic总线-quartusii realtime pcf8563 project and code and IIC verilog hdl
counter2
- 附件包括两个内容1.采用Verilog编写的的十进制计数器的ISE工程2.代码文档一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 written by Verilog decimal counter of the ISE project a 2 code document. The software platform is ISE13.3, the hardware platform is Spart
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document a 3 principle that 4 instructi
Adder_12bit
- 带进位的12位宽超前进位加法器，可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.
trafficlights
- Verilog实现的交通灯功能工程 在Quartus环境-traffic lights of Verilog
Example-s5-1
- “\Example-s5-1\des” 目录下为设计工程，其设计输入采用Synplify预先编译好的.vqm网表 “\Example-s5-1\source”目录下为设计的源代码，这里只给出了Verilog语言实例，仅供读者参考 “\Example-s5-1\source \area_opt”目录下为面积优化的代码 “\Example-s5-1\source \perf_opt”目录下为性能优化的代码 “\Examp
async_fifo_prj
- Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code
SinGen
- 使用Verilog编写的正弦波生成工程，使用ROM核产生，利用mif文件-Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file
ft245bmusb
- 基于ft245的Verilog驱动编程，有具体的代码和工程，接上硬件即可使用-Ft245 based on Verilog-driven programming, there are specific code and engineering, connected hardware to use
counter
- verilog 写的一个增减计数器的例子，可用于位同步时钟提取中，已经经过验证，可直接添加到自己的工程中。-Verilog write an increase or decrease the counter example, can be used to extract a synchronous clock, has been validated and can be directly added to your project.
video_center_scan_scaler_alpha_blend
- 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discr iption
ethmac10g_latest.tar
- ethmac10g_latest是用verilog编写的10gbps的以太网mac，对工程开发非常有用！-ethmac10g_latest is written in verilog 10gbps Ethernet mac, very useful for the development of the project!
RISC_CPU
- 这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。-This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested o
fifo
- FIFO源码以及测试文件基于ISE14，Verilog语言编写，全部工程。-FIFO based on source code and test files ISE14, Verilog language, the whole works.
flappybird
- 这是我练手时写的一个小游戏，是基于flappybird游戏原理制作的，用硬件完成其功能。主要用Verilog语言完成功能描述，通过ps2键盘的空格键控制飞翔，在VGA上进行显示。本工程已在basys2实验开发板上进行验证，画面略显粗糙，见谅。-This is what I wrote when practiced hand of a little game, is based on the principle of making flappybird game, with the hardwar
VendingMac
- Verilog实现的自动售货机，使用有限状态机进行处理。包括Modelsim和Spnplify的综合工程。-Verilog realize vending machines, using a finite state machine for processing. Including integrated engineering and Spnplify of Modelsim.
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
addafilter
- 基于NIOSii的数字滤波器，包括AD和DA的读取输出部分，包括C语言源码和verilog源工程-digital filter based on Nios2
TIMER
- 用Verilog语言模拟的数字时钟的功能，时分秒工能都有，适合做毕设，完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete