搜索资源列表
fifo
- Verilog HDL实现复杂逻辑设计FIFO-Verilog HDL to achieve FIFO
Publictelephone
- 用verilog设计的一个公用电话计费系统的设计文档-With verilog design of a public telephone billing system design documents
RS
- RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
verilog.
- verilog程序设计实例，非常详细，有注释-verilog program design, very detailed, annotated
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
irda_rx
- 红外收发器接收模块，很好很强大。采用Verilog设计并用Modelsim进行仿真，功能完全正确。-Infrared transceiver receiver module, very very strong. Using Verilog design and simulation using Modelsim, function entirely correct.
Verilog-HDL-design
- verilog方法逻辑设计教程，教会复杂电路设计的基本-verilog tutorial method of logic design, circuit design of the basic church complex
Verilog-FIFO
- 可综合的Verilog FIFO存储器，可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
adda
- 这是一个设计良好用来采集数据的adda verilog 程序，部件完整，他可以设定 同步异步时序 可以设定 采集速度 等诸多参数-This is an adda verilog data collection procedures, components is complete
fdivision
- 简单的分频器的VERILOG设计，带测试代码。初学者适用。-Simple prescaler VERILOG of design, with the test code. For beginners.
yuanchengxu
- 基于Verilog HDL的通信系统设计-Design of communication system based on Verilog HDL
FPGACPLDXilinx-ISE-5.X--verilog
- FPGACPLD设计工具Xilinx ISE 5.X使用详解》配套光盘-FPGACPLDXilinx ISE 5.0--verilog
Verilog-xiayuwen-text
- Verilog数字系统设计教程（夏宇闻）例题源程序-Verilog digital system design course (XiaYuwen) sample source program
Verilog-HDL-synthesis(2e)
- Verilog HDL数字设计与综合（第二版）-Digital Design and Verilog HDL synthesis
example-of-verilog-design
- verilog的大量实例，包括一些常用的数字电路的设计-verilog a large number of examples, including some commonly used digital circuit design, very practical
Verilog
- 夏宇闻 Verilog数字系统设计教程 源码,包括书中的全部内容，非常实用-Xia Yu Wen Verilog digital system design tutorial source code, including the entire contents of the book is very practical
FPGA-verilog-matlab
- 《无线通信FPGA设计》一书中例子的Matlab及verilog代码，非常详细-"Wireless FPGA design," a book example of Matlab and verilog code, very detailed
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,