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ethernet-verilog
- 非常详细的千兆以太网MAC verilog代码,可以供硬件设计时有关网络的开发参考-Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference
Verilog
- Verilog HDL高级数字设计 上海交大微电子学院 何卫锋 蒋剑飞-Advanced Digital Design Verilog HDL He Weifeng Jiang Jianfei, Shanghai Jiaotong University School of Microelectronics
HDB3编解码器课程设计
- 对HDB3码型基本原理和特性的认识、对Quartus Ⅱ软件的熟练操作、对Verilog HDL的掌握和应用,这些知识都是进行电子设计的基本知识和能力,只有基础知识和能力扎实了,才能更好的进行更高层次的电子设计,所以这个设计也是对电子设计基本能力的很好的锻练。
cal
- verilog设计计算器顶层模块,无下层模块需自行添加-verilog based calculator
LCD12864_verilog
- fpga控制LCD屏幕全部用verilog设计可用,通过仿真测试-FPGA controls the LCD screen all the Verilog design are available through the simulation test
Verilog-coding-style-in-asic-design
- 该文档描述了ASIC芯片设计的verilog编程规范,这对芯片的正常流片极重要。-This document describes the verilog coding style in asic design.
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码,实验资料,包括原理和代码,在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Buzzer-for-verilog
- 在FPGA上设计实现控制蜂鸣器,程序来自实验开发,验证通过。-Designed and implemented in the FPGA to control the buzzer, the program from experimental development and validation through.
Verilog-crossover-design
- Verilog分频器设计分频器是FPGA设计中使用频率非常高的基本单元之一-Verilog crossover design
verilog-uart-rs232
- verilog HDL 描写的uart程序 由PC端接收然后+1返回 等等 东南大学09级4系综合课程设计-verilog HDL descr iption uart program Received by the PC side and then+1 back。 SEU..
Verilog
- 无线通信FPGA设计_代码 无线通信FPGA设计_代码-FPGA design _ code wireless communications wireless communications wireless communications FPGA design _ code _ code for FPGA design
cadence-verilog-a-language-reference
- 这个是cadence公司的verilog-a学习手册,非常全面,是模拟集成电路设计的好助手-This is the company' s cadence verilog-a study manual, very comprehensive, is the analog integrated circuit design, a good assistant
Verilog-HDL--MODEL
- Verilog HDL程序设计教程verolog代码设计,包含各种基本代码-Verilog HDL programming tutorial verolog code design, includes a variety of basic code
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料,这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程,感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
lab16
- 利用verilog设计一个数字秒表电路。可以通过按键开始计时,计时完毕,清零设定。-Use verilog design a digital stopwatch circuits. Can be key will begin counting is completed, clear the settings.
verilog-HDL-code
- Verilog HDL程序设计实例详解的源代码-verilog HDL code
IIC-fpga-verilog
- 基于fpga的IIC设计,verilog-IIC fpga-based design, verilog
Verilog-programming-example
- Verilog的135个经典设计实例.pdf,一步一步学习,实用性非常强。-Verilog programming
RS(255 239 )编码器 Verilog HDL 实现
- 对于 RS 编码器的设计,常用的编码算法有 2 类,一类是 Berlekamp 算法,另一类是典型编码算法。Berlekamp 算法常用于数据速率要求不是很高的环境下,而典型编码算法具有电路实现结构简洁,占用硬件资源少等优点,因此,采用典型编码算法来实现编码器。
华为verilog编程规范
- 华为verilog编程规范,本规范规定了Proverilog编码规范,即采用verilog代码设计时的代码书写规范。本规范适用于逻辑芯片开发中使用verilog语言作为RTL级设计语言。