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verilog-hdl
- 本设计是以四路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。它以Verilog HDL硬件描述语言作为平台,结合动手实验而完成的-The design is based on four basic concepts answer. From the practical application, the use of electronic design automation (EDA) technology, using a prog
spi
- SPI 从机verilog设计,验证通过!-SPI interface slave verilog
QAM161
- 一个QAM16调制方式的verilog设计,包括4个verilog源代码,能够构成一个完整的QAM调制器-A QAM16 modulationVerilog design , including four verilog source code, which can form a complete QAM modulator
Verilog-Digital-control
- Verilog HDL数字控制系统设计实-冼进-源代码-4469-Verilog HDL digital control system design implementation- Xian Jin- source code-4469
Verilog
- Verilog初学者使用,各种verilog的典型电路设计。包括状态机、CRC校验等。-Verilog beginners, abundant examples
Verilog-implementation-PWM-
- verilog生成PWM的硬件设计-The development of a use Verilog implementation PWM hardware instance
Verilog-VGA
- 这是我用Verilog 在ISE软件编写设计的一个基本的VGA显示程序,需要使用Spartan 3E来实现VGA程序在显示器上显示,显示图形,静态图形600*800分辨率,将屏幕四等分,并分别显示不同的颜色,建议初学者参考-This is a basic VGA I used to write Verilog design in ISE software display program, you need to use Spartan 3E to implement the program on
start_lab4
- 用Verilog设计一个时间基准电路和带使能的多周期计数器,并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
PS2_SOC1
- 用Verilog 设计了PS2 键盘 模块。 在altera公司的Cyclone系列测试了。 正常动作。包含者 doc软件,说明了动作原理。-This is a state-machine driven serial-to-parallel and parallel-to-serial interface to the ps2 style keyboard interface.
chuanb
- 这是紫外光大气通信PPM方法调制设计系统中的串并装换程序,用Verilog设计并编译成功,希望对大家有帮助-The method of ultraviolet communication atmosphere PPM modulation design system of string and put in procedures, using Verilog design and compile successfully, I hope it can help you
verilog
- verilog 常用模块,包含设计模块和测试模块,如有ram, lifo等-verilog useful blocks
cpu_1
- 用verilog设计五级CPU的框架,需要自己另行补充指令,可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
verilog-traffic
- 模拟一个简单的十字路口交通灯(各个只有红绿黄灯,没有转弯灯)。交通灯一共有4 个状态,一是倒计时60 秒,同时亮南北方向绿灯、东西方向红灯;二是倒计时5 秒,同时数码管闪烁显示‘0’,同时亮南北方向红灯、东西方向黄灯;三是倒计时30 秒,东西方向亮红灯、南北方向绿灯;四是倒计时5 秒,数码管闪烁显示‘0’,东西方向亮黄、南北方向红灯。四个状态循环就构成了一个简单的交通灯(未了降低难度,我们设计简化交通灯,与真实情况不太一样)。-Simulate a simple intersection tra
Verilog-example3
- verilog实例分析第三部分,通过实例分析讲解有限状态机的设计过程。-The third case study verilog part, by an example to explain the finite state machine design process.
32-bit-division-design-In-Verilog
- 32位除法器,基于状态机设计,使用Verilog实现-32-bit division based on state machine. Using Verilog
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码,可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
cpu-7-verilog
- 多周期cpu设计asadsdddasd-multi cpu design
HUAWEI-Verilog
- 华为公司的Verilog HDL典型电路设计指导,仅供公司内部使用,内含全部源码,有很大的硬件设计指导意义。-Huawei s Verilog HDL typical circuit design guidance for internal company use, containing all the source code, there are a lot of hardware design guide
verilog
- 描述了出租车计费系统的设计功能,包括计时、计费等等,包括了出租车的所有计费功能-Describes the design of the taxi billing system functions, including time, billing, etc., including all the pricing function of the taxi
case-and-if-programing-in-verilog
- Case语句和if语句在电路设计中的注意事项,各种产生锁存器的原因分析,以及原代码-case and if using in verilog