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bingo_spi_test
- 利用SPI实现FPGA和外设之间的通信。经过Modelsim仿真验证。（为FPGA设计技巧与案例开发详解一书源码）(Using SPI to implement communication between FPGA and peripheral. After Modelsim simulation verification. (for FPGA design techniques and case development detailed explanation of a book source
8051-master
- 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU inte
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)
通信IC设计 下 ,李庆华著 ,P537 ,2016.04
- 通信中FPGA中通信过程 与 matlab verilog的部分实现(the communication process via matlab and fpga)
基于FPGA的高斯随机数发生器的设计与实现_徐新才
- 介绍了一种利用FPGA硬件平台生成高斯随机数的算法。(An algorithm for generating Gauss random numbers using FPGA hardware platform is introduced)
traffic
- 交通灯设计，用verilog语言来实行，不包含设计原理图(aknsh s kjsf kwfh jfls ljfsl s lfjls jlsj ls jlf l ljfs ljljl f jljl ljjlsfj ljlsfj ljsflhig)
lab1 Vivado Design Flow
- 适用于对verilog语言的初步学习，本文本就对RTL的编写，功能仿真，实现，布线，综合，以及生成比特流等环节进行了初步的描述。适合初学者学习。(For the preliminary study of Verilog language)
IIR滤波器的FPGA设计
- 基于verilog hdl语言对IIR滤波器设计(Design of IIR filter based on Verilog HDL language)
Chuankou
- 实现8位串口的接收和发送模块，将串口接收和发送模块分成了几个小模块进行设计。方便之后的bug的修改。(Receiving and sending module of 8 bit serial port)
vote
- 设计一个100人投票器，超过70人算通过，用verilog语言设计(Design a 100 person voter, more than 70 people passed, using Verilog language design)
jishi
- 用verilog语言设计了一个万年历，包括闰年判断，仿真正确(A calendar is designed with Verilog language, including leap year judgment, simulation is correct)
fenpin
- 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
traffic2
- 数电课程设计，交通灯，基于Quartus II编写(Digital electric course design, traffic lights)
clock_shiyan
- 数电课程设计，数字时钟，基于Quartus II设计(Digital electric course design, digital clock)
CPU
- 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)
遥控器接收解码电路
- 设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial
oscillo_1
- 简单数字示波器的verilog设计,涉及到时钟同步，FIFO的配置和使用，非常适合用来学习FPGA以及熟悉quartus II 软件。(digital oscilloscope design)
SystemVerilog for Design(Second Edition)
- 本文档用于使用systemverilog系统硬件描述语言做ASIC设计，深入浅出，易懂(The doc is using systemverilog system harward descr iption language to do ASIC design.The doc is easy to read,for new bird in this fact.)
PWM
- 利用Verilog语言设计一个PWM控制器，实现：控制器输入时钟1MHz；控制器输出脉冲周期1kHz，脉宽最小调节步长0.1%。(The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustme
方波产生
- 设计一个方波产生电路，并进行功能验证和时序验证。(A square wave generation circuit is designed, and function verification and time series verification are carried out.)