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signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
mipsinverilogandvhdl
- mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
controller
- MIPS处理器的控制verilog代码,可综合,可仿真,属硬件描述语言,集成电路设计代码
H.265_X86_DEMO
- ZPAV(小名H265),凝集 形态,分形,模糊,小波,数字图象处理学 等数学精华, 我 感受到了她的威猛的能量,听到了她的呐喊!她如春雷, 震撼着 单薄数学(DCT+ME+HUFFMAN等)的MPEGxx和H26xx的古老统治! ZPAV (H.265) 基本算法 :V0,V6 用了 二维小波;V8 用了 三维小波;V9 用了 四维小波; P帧(ME) 使用了 小波域运动估计;声音(A0,A6,A8,A9), 运动矢量(MV) 使用了 广义小波。 Z
mips_verilog.rar
- verilog语言实现的基于MIPS体系结构的微处理器程序,一个时钟周期执行一条指令。,verilog language MIPS-based microprocessor architecture, an implementation of a clock cycle instructions.
mipsdesign
- mips核代码,Verilog写的,希望对大家有用-mips core code, Verilog written
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
multi_cpu
- 多周期CPU,mips指令集,实现了部分指令,包含测试程序,verilog-Multi-cycle CPU
liyamin_slides
- 基于MIPS的运算器设计,内附详细设计文档,包含设计文档和使用手册,主程序,测试程序,还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条,用AHDL编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and user manual,
ALUC
- 用verilog语言中xilinx平台上实现single ALU,包括alu的基本MIPS指令运算,ALU control的实现-Xilinx verilog languages with the platform to achieve single ALU, including the basic MIPS instructions alu operations, ALU control implementation
simplemips
- simple MIPS with verilog
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
CPU
- 多周期CPU设计,使用Verilog HDL语言编程,实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
CPU
- mips系列,CPU的Verilog语言设计,自己写的-mips series, CPU of the Verilog language design, to write their own
MIPS_cpu_verilog
- 带流水线的类MIPS CPU verilog源代码-With lines of class MIPS CPU verilog source code
MIPS_CPU_OR2000
- MIPS架构的开发的CPU软核OR2000 verilog实现,MIPS体系结构cpu设计入门参考-The development of the MIPS architecture CPU soft core OR2000
MIPS_Project
- Verilog Source File. MIPS Processor Pipelining
multi_cycle_Verilog
- this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less th
SourceCode
- That s a bunch of ALU control code for MIPS pipelined in Verilog!
MIPS指令verilog实现
- 单周期MIPS指令处理器能在一个时钟周期内完成add、sub、and、or、sw、lw、beq、j等一条MIPS指令的处理。 单周期MIPS指令处理器包括以下几部分电路:指令存储器、数据存储器、寄存器堆、算术逻辑运算单元、控制电路。 指令存储器:保存处理器的指令,起始地址为0x00400000; 数据存储器:保存处理器的数据,起始地址为0x10010000; 寄存器堆:32个32bit寄存器; 算术逻辑运算单元:完成各种运算; 控制电路:产生处理器的控制信号,包括PC生成。