搜索资源列表
leds
- 这是一个在xilinx的开发环境EDK上，点亮LED灯的代码示例-This is a xilinx EDK development environment, code samples, lit LED lights
VHDL_uart
- 用xilinx的FPGA-spartan3E实现uart，固定波特率9600，偶校验，系统时钟50MHz，能够实现将从串口调试助手发送到FPGA的数据重新发回串口调试助手-using xilinx s FPGA-spartan3E to implement uart with a baudrate of 9600, even parity check. The system frequency is 50MHz.It can turn the data from serial assistant
imageprocess
- 典型的图像采集verilog代码，开发板源码-this is typical image process code,provided by xilinx developmentpacadge
08_Audio_demo
- 这是赛灵思在FPGA上连接声音设备的bit流文件（在Xilinx platform Studio上运行），还包括相关的说明文档-This is the connecting sound equipment on Xilinx FPGA bit stream files (running) on Xilinx platform Studio also includes related documentation
PluseMaker
- 秒脉冲发生器 频率可调 带数码管显示 带约束文件 配合 Xilinx FPGA-Second pulse generator frequency is adjustable with digital display
fpga_nes-master
- 这是一个完整的红白机nes游戏fpga实现，经测试可用，使用ise14.1以上版本的工程文件，开发板使用的是xilinx spartan6-This is a complete NES nes games fpga implementation, the test is available, use ise14.1 above version of the project file, the development board using xilinx spartan6
Lab05-Chipscope_Debugging_13_1_1
- xilinx fpga microblaze Embedded Chipscope DebuggingThis is the fifth tutorial in a series of training material dedicated to introducing engineers to creating their first embedded designs. These tutorials will cover all the required steps for creating
bw_scoresource
- This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
xc3san_bsdl
- xilinx FPGA IBIS模型,系统集成FPGA 分析必备工具-xilinx FPGA IBIS model is an indispensable tool for system integration FPGA analysis
spartan3an_ibis
- xilinx FPGA IBIS模型,系统集成FPGA 分析必备工具-xilinx FPGA IBIS model is an indispensable tool for system integration FPGA analysis
ddc_v5
- wcdma数字下变频 是采用matlab 里面的simulink仿真工具和xilinx 的system generator 工作开发的，可以直接运行的，非常有参考价值-wcdma digital down conversion is used inside matlab simulink simulation tools and working to develop a xilinx system generator, and can run directly, very useful
ofdm_baseband_design_basedon_fpga
- 基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 -this is source code from a book
V-6-FPGA-Configure-Guide
- Xilinx公司的Virtex-6配置指南，是详细的官方指南-Virtex-6 configuration guide Xilinx company, is the official guide
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
FIR
- 使用Verilog语言编写的FIR滤波器,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog
vga_640x460_spirte
- 使用Verilog语言编写的vga显示条纹的程序,可以在显示器上显示彩带,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language program vga display stripes, ribbons can be displayed on the monitor in the Xilinx Spartan-6 run through, is a very good program Verlog
SRAM
- 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
brom_16x8
- 使用Verilog语言编写的ROM读写程序,使用IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-ROM using Verilog language literacy program, the use of IP core in Xilinx Spartan-6 run through, is a very good program Verlog
bram_16x8_top
- 使用Verilog语言编写的RAM程序,可以双向读写,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-RAM using Verilog language program, you can bi-literacy, in the Xilinx Spartan-6 run through, is a very good program Verlog
shuzibiao
- xilinx下使用vhdl编写数字表 具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s -xilinx vhdl prepared using digital watch with a start, reset, pause, pause, continue after the timer function can display the seconds counting time accurate to the second